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參數(shù)資料
| 型號： | M5M5V408BTP-85LW |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 85 ns, PDSO32 |
| 封裝： | 0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-32 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 118K |
| 代理商： | M5M5V408BTP-85LW |
MITSUBISHI ELECTRIC
M5M5V408BFP,TP,RT,KV
revision-K2.0e, ' 99.03.10
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address
Output disable time after S high
5
t
CR
t
a
(A)
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
30
30
85
60
0
70
70
35
0
0
5
5
1TTL
CL
DQ
70
10
5
10
70
70
35
25
25
25
25
70
55
0
65
65
35
0
0
5
5
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
85
10
5
10
85
85
45
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
V
IH
=2.4V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Transition is measured ±500mV from
steady state voltage.(for t
en
,t
dis
)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
AC ELECTRICAL CHARACTERISTICS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
(2) READ CYCLE
Symbol
Parameter
Limits
Units
Max
Min
Max
Min
Read cycle time
Address access time
Chip select access time
Output enable access time
(3) WRITE CYCLE
Symbol
Parameter
Limits
Max
Min
Max
Min
Units
Write cycle time
Write pulse width
Address set up time
Address set up time with respect to W high
Chip select set up time
Data set up time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
Supply voltage
Input pulse
Fig.1 Output load
Including scope and
jig capacitance
M5M5V408B
FP,TP,RT,KV,KR-70
M5M5V408B
FP,TP,RT,KV,KR-85
M5M5V408B
FP,TP,RT,KV,KR-70
M5M5V408B
FP,TP,RT,KV,KR-85
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