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參數(shù)資料
| 型號： | M600P622.0800 |
| 元件分類： | XO, clock |
| 英文描述： | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 622.08 MHz |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 352K |
| 代理商： | M600P622.0800 |
M600 Series
Preliminary Specifications
Micro Networks Corporation 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
Output Disable (OD) & External Clock
Input (CLKIN)
Bringing Output Disable (OD, pin 21) low allows a test
signal to be applied to the device’s Clock In (CLKIN,
pin 4). This applied clock signal will be fed through
the device to its differential clock outputs. This mode
of operation can be employed to facilitate onboard
testing. The applied external clock signal can be
PECL or a sinewave (up to 1Vp-p, AC coupled. Clock
Input (CLKIN) is internally biased to VBB (Vcc –1.3V).
Setting Output Disable (OD, pin 21) low disables the
clock outputs at pins 23 and 25 forcing pin 23 to a
logic “high” and pin 25 to a logic “l(fā)ow”. The threshold
for Output Disable is set to 1.4V above V
EE
. Output
Disable should not be driven above the mid value of
the supply. During normal operation, Output Disable
should be left floating (use with an open collector or
3-state gate for operation under logic control).
If the output disable feature is used in normal
operation without an external signal applied to Clock
In (pin 4), Clock In should be tied low to ground
through a 10K Ohm resistor to avoid unwanted
signals on the clock output lines.
Modulation Bandwidth Control
An optional capacitor connected from pin 17 to
ground can be employed to reduce the modulation
bandwidth when the M600 is used in narrow
bandwidth PLL applications. The modulation
bandwidth will be approximately (1/12000 x C) Hz,
where C is equal to the capacitance value in Farads.
If the capacitor is not used and pin 17 is left open, the
modulation bandwidth will be approximately equal to
the nominal frequency divided by 1200.
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY TRANSLATION
APPLICATIONS INFORMATION
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