MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
7
SERIAL REGISTER INFORMATION
(cont.)
Sub-
address
setting
0
0/1
1
0/1
2
1/0
3
0/0
4
0/1
5
0/1
6
1/0
7
0/0
0
0/0
1
0/0
2
0/0
3
1/0
4
0/1
5
0/0
6
0/0
7
0/0
0
0/1
1
0/0
2
0/0
3
1/1
4
1/0
5
1/1
6
7
0
1
2
3
4
5
6
7
0
1
Bit No.
Reference
Register name
Function
0Bh
vya (0)
vya (1)
vya (2)
vya (3)
vya (4)
vya (5)
vya (6)
vya (7)
hxa (0)
hxa (1)
hxa (2)
hxa (3)
hxa (4)
hxa (5)
hxa (6)
hxa (7)
hya (0)
hya (1)
hya (2)
hya (3)
hya (4)
hya (5)
ext-bhsel (0)
ext-bhsel (1)
adj (0)
adj (1)
adj (2)
adj (3)
hadj (0)
hadj (1)
hadj (2)
hadj (3)
disp
bgc
Setting of display period (vertical);
{vya<7:0>} line
[44h/33h (1/9-1/16 sizes)]
0Ch
Setting of display start position (horizontal);
{hxa0<7:0>
×
4
×
70ns+12.8}us
[08h-10h (1/9-1/6 sizes) when displayed at the upper left]
0Dh
Setting of display period (horizontal);
{(hya0<5:0>-1)
×
4
×
70}us
[38h/29h (1/9 - 1/16 sizes)]
1
1
0
0
1
0
1
1
1
1
1
0
Selection of sync input for burst clock;
HD pin [0 or 1], VD pin [2], internal analog [3] [3 setting]
0Eh
Adjustment of sub-screen display-starting horizontal position; [4h setting]
70ns/step
Min. 280ns [0h], center 0ns [4h], +770ns [Fh]
Adjustment of supplementary BGP position; [Normally Fh setting]
Parameter to adjust PIP Y output signal clamping position to main Y input signal
pedestal (when 03h<4>(bgpmsel) = 1)
5.6us[0h], 6.6us [Fh] (pulse width: 2.6us) from the front end of horizontal sync
0Fh
Display control; PIP display OFF/ON [0/1] (ineffective at background)
Background display control; OFF/ON [0/1]
Authorization of addition of sync when missing main source is detected; OFF/
ON [0/1]
2
0
dofc
3
4
5
6
7
1
1
1
1
0
y-offset (0)
y-offset (1)
y-offset (2)
y-offset (3)
y-offset (4)
Setting of luminance signal output DC offset;
Set pedestal level within a range of 32 digits/256 digits (complements of 2, "-16fl
to +15fl" or "0", provides image data bottom values. It serves fine adjustment of
brightness.)