參數(shù)資料
型號(hào)： M65676FP
廠(chǎng)商： Mitsubishi Electric Corporation
英文描述： DIGITAL NTSC/PAL ENCODER
中文描述： 數(shù)字的NTSC / PAL編碼器
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 83K
代理商： M65676FP
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
5
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
CCIR656 Interface
PXCLK=27.0MHz
Cb/Y/Cr=8-bit/27.0Mbps
Y=8-bit/27.0Mbps
16-235 straight-binary-data
Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75 Mbps)
16-240 128 offset-binary-data
Active video area525/60=720-pixel￥480 line/frame
(22/284 line-263/525 line)
625/50=720-pixel￥576 line/frame
(23/336 line-310/623 line)
Vertical blanking Interval
525/60=1/264-9/272
Digital field 1 (ODD)=4-265
Digital field 2 (EVEN)=266-3
625/50=624/311-22/335
Digital field 1 (ODD)=1-312
Digital field 2 (EVEN)=313-625
Horizontal blanking Interval525/60=276CLK (0H=32CLK)
EAV=1-4CLK/SAV=273-276CLK
625/50=288CLK (0H=24CLK)
EAV=1-4CLK/SAV=285-288CLK
The input data (X), except the active data in the above support
format, are clipped as shown below;
8/16-bit CCIR601 Interface
Y
: X￡16 16
X
≥
235235 (Whole period)
Cb/Cr : X￡16 16
(U/V)
X
≥
240240 (Whole period)
CCIR656 Interface
Y
: X￡16 16
X
≥
235235 (Active video period)
X 16 (Blanking period)
Cb/Cr : X￡16 16
(U/V)
X
≥
240240 (Active video period)
X 128 (Blanking period)
Digital Multiplexing
The input pixel data described in 4.1.1.1 are de-multiplexed, then Y,
Cb,Cr and Y, U, V signals will be converted to each 8-bit parallel
data. After the above conversion, 6.75Mbps Cb, Cr/U, V data are
interpolated at a double clock rate of 13.5Mbps.
PXCLK Processing
PXCLK is generated from the 27.0MHz system clock according to
the appropriate selected format and the clock signal for Y, Cb, Cr/Y,
U, V data de-multiplexing is also generated.
OSD Interface
Color Look-up Table (CLT)
The built-in CLT can be equivalent to 4bit￥8 colors, so that the
reproduced colors are 8/4096.
The setting ranges and the signal levels in the overlaying of Y, Cb
and Cr each are shown below;
Y :Setting range=1 (h) to F (h) : straight-binary data
Signal Level=10 (h) to F0 (h) : straight-binary data
Cb/Cr : Setting range=1 (h) to F (h) : 8 offset-binary data
Signal level=10 (h) to F0 (h) : 128 offset-binary data
OSD Control
Overlaying the appointed data on the video signal from MPEG is
possible by inputting the address data to the CLT in synchronization
with OSDCLK, H-sync and V-sync. The overlaying is prohibited in
case CLT address is set to 7 (h).
The OSD control specifications are shown below;
OSDCLK= selectable 13.5MHz or 6.75MHz
selectable continuous or discontinuous
(pausing during H-sync) clock
Color Signal Blend=Maximum 3 colors are allowed to be set.
The data of CLT addresses 0 (h) to 2 (h) are
dedicated to color blending.
The blend ratio is fixed by 1:1 and blend
mode is selectable between Y/Cmix and Ymix
mode.
Y/Cb/Cr to Y/U/V Converter
C-sync Addition
The sync signal, set up in the register, is added to Y signal
according to C-sync timing generated from H-sync/V-sync. Typical
sync height, set up in the register, is calculated by the following
equations;
Sync level={(White peak input level-16)￥2.5￥Xsync (IRE)}/100
In the case ofNTSC: {(235-16)￥2.5￥40}/100=219 (DB
H
)
PAL
: {(235-16)￥2.5￥43}/100=235.4 (EB
H
)
Note: Xsync=Output sync level (IRE)
Set-up Control (NTSC)
In the NTSC signal generation mode, three set-up modes are
possible according to the register.
Selectable set-up modes are;
Mode 0 : Set-up0 IRE
Mode 1 : Set-up+7.5 IRE
Mode 2 : Set-up-7.5 IRE
Cb/Cr to U/V Conversion
The Cb/Cr data are converted into the U/V data by the following
equations;
U=0.493￥Cb/0.564
V=0.877￥Cr/0.713
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