參數(shù)資料
型號(hào): M66239FP
廠商: Renesas Technology Corp.
英文描述: High Speed Standard Clock Generator With Frequency Synthesizer
中文描述: 高速標(biāo)準(zhǔn)時(shí)鐘發(fā)生器,頻率合成器
文件頁(yè)數(shù): 14/24頁(yè)
文件大?。?/td> 312K
代理商: M66239FP
M66239FP
Rev.1.00 Mar 16, 2005 page 21 of 23
After Power-On Procedure
After power-on, M66239FP status is unknown. Following procedure must be done.
1. VCC power-on
2. After Vcc and input clock frequency is stable, set the FSET[2:0].
3. Reset pulse input.
Input more than MCLK 1000 clock cycle from FSET setting is completed to RESET set to "H" level.
4. Serial resister set.
5. After input MCLK clock till PLL lockup time (Tplllock), input twice TR pulse.
Input more than 100 cycle MCLK clocks between 1st. TR and 2nd. TR.
6. After that, sync clock will be outputted from M66239FP.
FSET<2:0> set (refer to page 20)
More than 1000 cycles
tw(RESET)
VCC
Serial
resister
MCLK
FSET
TR
RESET
CKO/CKOB/PULSE
More than 100 cycles
tsp
tss
tsp
Tplllock
tss
Note: 1. In case of change the resister set after complete above power on procedure, the new resister set value reflects
after the at least more twice TR pulse input. And when changing register 4, for the center frequency purpose
to be changed, the locked time of PLL must be wait. Also,there is not a problem even if a trigger signal is
entered before the PLL lock after changing register 4. When changing a register except register 4, not need
to wait locked time of PLL.
Setting
completed
Input clock frequency
is stable
Serial resister set (refer to page 15 to 17)
Figure 11 After Power-On Procedure
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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