參數(shù)資料
型號: M66239FP
廠商: Renesas Technology Corp.
英文描述: High Speed Standard Clock Generator With Frequency Synthesizer
中文描述: 高速標(biāo)準(zhǔn)時鐘發(fā)生器,頻率合成器
文件頁數(shù): 19/24頁
文件大?。?/td> 312K
代理商: M66239FP
M66239FP
Rev.1.00 Mar 16, 2005 page 4 of 23
Pin Description
Pin Name
I/O
Function
MCLK
I
Input clock.
SCLK
I
Serial resister clock input.
SENABLE
I
Serial resister enable input.
H level: disable, L level: enable
SDATAIN
I
Serial resister data input.
RESET
I
System reset input. When set to "L", system reset function.
Reset function initialize all resister data to the default settings.
FSET<2:0>
I
Frequency range settings correspond to MCLK frequency.
MODE
I
Trigger edge polarity (positive/negative) select.
H level: negative edge mode, L level: positive edge mode
TR
I
Trigger input for clock outputs.
CLKO
O
Continuous clock output. CLKO is asynchronous clock output to trigger.
CKO
O
Sync. clock output. Synchronized with trigger signal.
CKOB
O
Sync. clock output. Synchronized with trigger signal.
CKOB is inverted clock of CKO.
PULSE
O
Sync. clock output. Synchronized with trigger signal.
PULSE is one-shot pulse synchronized with CKO.
SDATAOUT
O
Serial resister data output.
OE
I
Output enable control.
H level: CKOB and PULSE will be disabled.
L level: All clock outputs will be enabled.
TEST<7:0>
I
Test control input. Set to "L".
TESTP<4:1>
TESTN<4:1>
O
Test control input. Set to open.
DVCC
DGND
I
Digital block VDD and GND.
AVCC
AGND
I
Analog block VDD and GND.
PLL VCC
PLL GND
I
PLL block VDD and GND.
DAC VCC
DAC GND
I
DA converter VDD and GND.
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參數(shù)描述
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