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參數(shù)資料
| 型號(hào)： | M66257FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| 中文描述： | 5120 × 8位× 2列內(nèi)存（先進(jìn)先出） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 122K |
| 代理商： | M66257FP |
1
M66257FP
515120
×
8- 8-BIT
×
2 2 LINE MEMORY (FIFO)
MIMITSUBISHI
DIDIGITAL ASSP
DESCRIPTION
The M66257FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word
×
8-bit double con-
figuration which uses high-performance silicon gate CMOS
process technology.
It allows simultaneous output of 1-line delay data and 2-line
delay data, and is most suitable for data correction over mul-
tiple lines.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
Memory configuration of 5120 words
×
8 bits
×
2 (dynamic
memory)
High-speed cycle ............................................. 25ns (Min.)
High-speed access ......................................... 18ns (Max.)
Output hold ........................................................ 3ns (Min.)
Fully independent, asynchronous write and read operations
Output ....................................................................3 states
Q
00
to Q
07
........................................................ 1-line delay
Q
10
to Q
17
........................................................ 2-line delay
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
32
MEMORY ARRAY OF
5120-WORD
×
8-BIT
×
2 CONFIGURATION
1-LINE DELAY DATA ONLY MEMORY/
2-LINE DELAY DATA ONLY MEMORY
W
R
R
W
31
30
WE
WRES
WCK
18
V
CC
28
V
CC
36
V
CC
WRITE
ENABLE INPUT
WRITE
RESET INPUT
WRITE
CLOCK INPUT
35
34
33
RE
RRES
RCK
READ
ENABLE INPUT
READ
RESET INPUT
READ
CLOCK INPUT
1 GND
19 GND
29 GND
27 26 25 24 23 22 21 20
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INPUT BUFFER
DATA INPUT
D
0
~
D
7
OUTPUT BUFFER
DATA OUTPUT
Q
00
~
Q
07
DATA OUTPUT
Q
10
~
Q
17
DATA INPUT
DATA OUTPUT
36
READ ENABLE INPUT
M
1
READ RESET INPUT
READ CLOCK INPUT
WRITE ENABLE INPUT
WRITE RESET INPUT
WRITE CLOCK INPUT
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
24
13
23
14
22
15
21
16
20
17
19
18
Q
00
←
Q
01
←
Q
02
←
Q
03
←
Q
04
←
Q
05
←
Q
06
←
Q
07
←
Q
10
←
Q
11
←
Q
12
←
Q
13
←
Q
14
←
Q
15
←
Q
16
←
Q
17
←
GND
V
CC
←
D
7
←
D
6
←
D
5
←
D
4
←
D
3
←
D
2
←
D
1
←
D
0
←
WCK
←
WRES
←
WE
←
RCK
←
RRES
←
RE
V
CC
V
CC
GND
GND
Outline 36P2R-A
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PDF描述 |
|---|---|
| M66258 | 8192 x 8-BIT LINE MEMORY |
| M66258FP | 8192 x 8-BIT LINE MEMORY |
| M66260FP | 8 x 4 CROSSPOINT SWITCH with MIXING FUNCTION |
| M66261FP | 6 x 5 CROSSPOINT SWITCH with MIXING FUNCTION |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66258 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66258FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66258FP(#TF0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66260FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8 x 4 CROSSPOINT SWITCH with MIXING FUNCTION |
| M66261FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:6 x 5 CROSSPOINT SWITCH with MIXING FUNCTION |
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