參數資料
型號: M68AF511AM70MC1
廠商: 意法半導體
英文描述: 4 Mbit (512K x8), 5V Asynchronous SRAM
中文描述: 4兆位(為512k × 8),5V的異步SRAM
文件頁數: 12/18頁
文件大?。?/td> 129K
代理商: M68AF511AM70MC1
M68AF511A
12/18
Figure 11. Chip Enable Controlled, Write AC Waveforms
Table 8. Write Mode AC Characteristics
Note: 1. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, t
WLQZ
is less than t
WHQX
for any given device.
Symbol
Parameter
M68AF511A
Unit
55
70
t
AVAV
Write Cycle Time
Min
55
70
ns
t
AVEH
Address Valid to Chip Enable High
Min
45
60
ns
t
AVEL
Address Valid to Chip Enable Low
Min
0
0
ns
t
AVWH
Address Valid to Write Enable High
Min
45
60
ns
t
AVWL
Address Valid to Write Enable Low
Min
0
0
ns
t
DVEH
Input Valid to Chip Enable High
Min
25
30
ns
t
DVWH
Input Valid to Write Enable High
Min
25
30
ns
t
EHAX
Chip Enable High to Address Transition
Min
0
0
ns
t
EHDX
Chip Enable High to Input Transition
Min
0
0
ns
t
ELEH
Chip Enable Low to Chip Enable High
Min
45
60
ns
t
ELWH
Chip Enable Low to Write Enable High
Min
45
60
ns
t
WHAX
Write Enable High to Address Transition
Min
0
0
ns
t
WHDX
Write Enable High to Input Transition
Min
0
0
ns
t
WHQX (1)
Write Enable High to Output Transition
Min
5
5
ns
t
WLEH
Write Enable Low to Chip Enable High
Min
45
60
ns
t
WLQZ (1,2)
Write Enable Low to Output Hi-Z
Max
20
25
ns
t
WLWH
Write Enable Low to Write Enable High
Min
45
60
ns
AI05914
tAVAV
tEHAX
tDVEH
A0-A18
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tWLEH
tELEH
tEHDX
DATA INPUT
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