參數(shù)資料
型號(hào)： M68AW127BM10MC6T
廠商： 意法半導(dǎo)體
英文描述： 1Mbit 128K x8, 3.0V Asynchronous SRAM
中文描述： 1Mbit的128K的× 8，3.0V異步SRAM
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 327K
代理商： M68AW127BM10MC6T
11/20
M68AW127B
Write Mode
The M68AW127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
t
AVWL
and t
AVEH
, respectively, and is determined
by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within t
WLQZ
of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
DVWH
before
the rising edge of Write Enable, or for t
DVEH
before
the rising edge of E1, whichever occurs first, and
remain valid for t
WHDX
or t
EHDX
.
Figure 11. Write Enable Controlled, Write AC Waveforms
AI05478
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E1
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
E2
tELWH
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M68AW127BM10N1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM
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M68AW127BM70MC1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM
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