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| 型號： | M68HC711D3CP1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 106/124頁 |
| 文件大小： | 5398K |
| 代理商： | M68HC711D3CP1 |
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SERIAL PERIPHERAL INTERFACE
8-4
TECHNICAL DATA
8.3.1 Master In Slave Out
MISO is one of two unidirectional serial data signals. It is an input to a master device
and an output from a slave device. The MISO line of a slave device is placed in the
high impedance state if the slave device is not selected.
8.3.2 Master Out Slave In
The MOSI line is the second of the two unidirectional serial data signals. It is an output
from a master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses to latch
the data.
8.3.3 Serial Clock
SCK, an input to a slave device, is generated by the master device and synchronizes
data movement in and out of the device through the MOSI and MISO lines. Master and
slave devices are capable of exchanging a byte of information during a sequence of
eight clock cycles.
There are four possible timing relationships that can be chosen by using control bits
CPOL and CPHA in the serial peripheral control register (SPCR). Both master and
slave devices must operate with the same timing. The SPI clock rate select bits,
SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,
SPR[1:0] have no effect on the operation of the SPI.
8.3.4 Slave Select
The SS input of a slave device must be externally asserted before a master device can
exchange data with the slave device. must be low before data transactions and must
stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault
circuit, write a one in bit 5 of the port D data direction register. This sets the SS pin to
act as a general-purpose output. The other three lines are dedicated to the SPI when-
ever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA set-
tings should be identical for master and slave. When CPHA = 0, the shift clock is the
OR of SS with SCK. In this clock phase mode, SS must go high between successive
characters in an SPI message. When CPHA = 1, SS can be left low between succes-
sive SPI characters. In cases where there is only one SPI slave MCU, its SS line can
be tied to VSS as long as only CPHA = 1 clock mode is used.
8.4 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises in
a multiple-master system when more than one SPI device simultaneously tries to be
a master. This error is called a mode fault. The second type of error, write collision,
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For More Information On This Product,
Go to: www.freescale.com
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