參數(shù)資料
型號： M68HC711D3CP1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 86/124頁
文件大?。?/td> 5398K
代理商： M68HC711D3CP1
PARALLEL I/O
6-2
TECHNICAL DATA
DDB[7:0] — Data Direction for Port B
0 = Corresponding port B pin configured for input only
1 = Corresponding port B pin configured as output
6.3 Port C
Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-
tiplexed mode, port C pins are configured as multiplexed address/data pins. During the
data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.
DDC[7:0] — Data Direction for Port C
0 = Input
1 = Output
6.4 Port D
The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and
SPI subsystems, or for bus data direction control. Port D can be read at any time. In-
puts return the sensed levels at the pin; outputs return the input level of the port D pin
drivers. If port D is written, the data is stored in an internal latch, and can be driven only
if port D is configured for general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow
on the bus in expanded and special test modes.
DDRB — Data Direction Register for Port B
$0006
Bit 7
654321
Bit 0
DDB7
DDB6
DDB5
DDC4
DDB3
DDB2
DDB1
DDB0
RESET:
00000000
PORTC — Port C Data
$0003
Bit 7
654321
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
S. Chip
or Boot:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
Reset configures pins as HiZ inputs
Expan.
or Test:
ADDR7/
DATA7
ADDR6/
DATA6
ADDR5/
DATA5
ADDR4/
DATA4
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
ADDR0/
DATA0
RESET:
Reset configures pins as multiplexed, low-order address/data I/O
DDRC — Data Direction Register for Port C
$0007
Bit 7
654321
Bit 0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
RESET:
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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