參數(shù)資料
型號: M69AW024BL70ZB8T
廠商: 意法半導體
英文描述: 16 Mbit (1M x16) 3V Asynchronous PSRAM
中文描述: 16兆位(1米× 16)3V的異步移動存儲芯片
文件頁數(shù): 25/29頁
文件大?。?/td> 429K
代理商: M69AW024BL70ZB8T
25/29
M69AW024B
Figure 22. Power-up Mode AC Waveforms - 3
Note: Both E1 and E2 must go High as V
CC
reaches V
CC
(min). If not, the timings provided in Power-Up Mode AC Waveforms 1 (
Figure 20.
)
or Power-Up Mode AC Waveforms 2 (
Figure 21.
) should be used to ensure proper operation.
Table 10. Low V
CC
Data Retention Characteristics
Note: 1. T
A
= –30 to 85°C
2. All other Inputs at V
IH
V
CC
–0.2V or V
IL
0.2V.
3. See
Figure 23.
for measurement points.
Figure 23. Low V
CC
Data Retention AC Waveforms
Symbol
Parameter
Test Condition
1
Min
Max
Unit
V
DR (2)
Supply Voltage (Data Retention)
E1 = E2
V
CC
–0.2V, or
E1
=
V
IH
and E2
=
V
IH
2.3
3.5
V
I
CCDR
Supply Current (Data Retention)
V
CC
= V
DR
, V
IN
0.2V or
V
CC
–0.2V,
E1
=
V
CC
–0.2V and E2
V
CC
–0.2V,
I
OUT
= 0mA
70
μA
t
CDR (2,3)
Chip deselected to Data Retention
Time
V
CC
=
2.7V
0
ns
t
R (3)
Operation Recovery Time
V
CC
=
2.7V
100
ns
V/
t
(3)
VCC Voltage Transition Time
0.2
V/μs
AI08054C
VCC
VCC min
E2
E1
0V
tEHEL
AI07408
DATA RETENTION MODE
V/
t
3.5V
tCDR
2.7V
2.3V
E1
E1 and E2
VDD – 0.2V or VIH(min)
Data Bus must be Hi-Z
VCC
E2
0.4V
VSS
tR
V/
t
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