參數(shù)資料
型號(hào)： M7020R-083ZA1T
廠商： 意法半導(dǎo)體
英文描述： 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述： 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁(yè)數(shù)： 18/150頁(yè)
文件大小： 996K
代理商： M7020R-083ZA1T
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M7020R
18/150
OPERATION
The following subsections contain command
(CMD and DQ Bus (command and databus), data-
base entry, arbitration logic, pipeline, and SRAM
control, and full logic descriptions.
CMD Bus and DQ Bus
CMD[8:0] carries the CMD and its associated pa-
rameter. DQ[67:0] is used for data transfer to and
from the database entries, which comprise a data
and a mask field that are organized as data and
mask arrays. The DQ Bus carries the SEARCH
data (of the data and mask arrays and internal reg-
isters) during the SEARCH command as well as
the address and data during READ and/or WRITE
operations. The DQ Bus can also carry the ad-
dress information for the flow-through accesses to
the external SRAMs and/or SSRAMs.
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask
field. The resultant value of the entry is ’1,' ’0,’ or
’X (don’t care),’ depending on the value in the data
and mask bits. The on-chip priority encoder se-
lects the first matching entry in the database that
is nearest to location '0.'
Arbitration Logic
When multiple Search Engines are cascaded to
create large databases, the data being searched is
presented to all search engines simultaneously in
the cascaded system. If multiple matches occur
within the cascaded devices, arbitration logic on
the search engines will enable the winning device
(with a matching entry that is closest to address “0”
of the cascaded database) to drive the SRAM bus.
Pipeline and SRAM Control
Pipeline latency is added to give enough time to a
cascaded system’s arbitration logic to determine
the device that will drive the index of the matching
entry on the SRAM bus. Pipeline logic adds laten-
cy to both the SRAM access cycles and the SSF
and SSV signals to align them to the host ASIC re-
ceiving the associated data.
Full Logic
Bit[0] in each of the 68-bit entries has a special
purpose for the LEARN command (0 = empty, 1 =
full). When all the data entries have bit[0] = 1, the
database asserts the FULL Flag, indicating all the
search engines in the depth-cascaded array are
full.
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PDF描述
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