參數(shù)資料
型號: M74HC593
廠商: 意法半導體
元件分類: 通用總線功能
英文描述: 8 Bit Binary Counter with Input Register (3-STATE)(8位二進制計數(shù)器帶輸入寄存器(三態(tài)))
中文描述: 8位二進制計數(shù)器的輸入寄存器(3態(tài))(8位二進制計數(shù)器帶輸入寄存器(三態(tài)))
文件頁數(shù): 7/12頁
文件大?。?/td> 274K
代理商: M74HC593
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
80
22
17
5.4
27
17
32
20
44
11
-55 to 125
o
C
54HC
Min.
Max.
140
28
24
Max.
175
35
30
Max.
210
42
36
t
PLZ
t
PHZ
3 State Output
Disable Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
R
L
= 1 K
ns
f
MAX
Maximum Clock
Frequency
50
4
4.4
22
26
3.6
18
21
MHz
t
W(H)
t
W(L)
Minimum Pulse
Width
(CCK, RCK)
50
100
20
17
100
20
17
125
25
21
75
15
13
125
25
21
50
10
9
0
0
0
5
5
5
10
125
25
21
125
25
21
160
32
27
95
19
16
160
32
27
60
12
11
0
0
0
150
30
26
150
30
26
195
39
33
110
22
19
195
39
33
70
14
12
0
0
0
5
5
5
10
ns
9
t
W(L)
Minimum Pulse
Width
(CCLR, CLOAD)
50
40
10
9
56
14
12
32
8
7
56
14
12
16
4
3
0
0
0
ns
t
s
Minimum Set-up
Time (CCKEN,
CCKEN, CCK)
50
ns
t
s
Minimum Set-up
Time
(RCKEN - RCK)
50
ns
t
s(H)
Minimum Set-up
Time
(RCK - CLOAD)
50
ns
t
s
Minimum Set-up
Time
(A to H - RCK)
50
ns
t
h
Minimum Hold
Time
50
ns
t
REM
Minimum Clear
Remuval Time
(CCLR, CLOAD)
50
ns
5
5
10
C
IN
Input Capacitance
Power Dissipation
Capacitance
5
pF
C
PD
(*)
19
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
AC ELECTRICAL CHARACTERISTICS
(continued)
M54/M74HC593
7/12
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