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參數(shù)資料
| 型號(hào)： | M74HCT7259B1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT |
| 中文描述： | 8位尋址鎖存器/解碼器/繼電器驅(qū)動(dòng)開漏輸出，輸出反相 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 90K |
| 代理商： | M74HCT7259B1R |
M74HCT7259
8BIT ADDRESSABLE LATCH/DECODER/RELAIS
DRIVER (OPEN DRAIN,INVERTING OUTPUT)
PRELIMINARY DATA
February 2000
I
LOWPOWERDISSIPATION
I
CC
=4
μ
A(MAX.) ATT
A
=25
°
C
I
COMPATIBLEWITH TTL OUTPUTS
V
IH
=2V (MIN) V
IL
=0.8V(MAX)AT5V
I
OUTPUTDRIVECAPABILITY
90LSTTLLOADS
I
HIGHCURRENT OPENDRAINOUTPUT UP
TO80mA
The M74HCT7259 is a high speed CMOS 8 BIT
ADDRESSABLE LATCH/DECODER fabricated in
silicon gate C2MOS technology. It has the same
high speed performanceof LSTTLcombined with
true CMOS low power consumption.
The M74HCT7259 has single data input (D) 8
LATCH inverted OUTPUTS (Q0-Q7), 3 address
inputs (A, B and C), common enable input
(ENABLE) and a common CLEAR input. To
operatethis device as an addressablelatch, data
is held on the D input, and the address of the
latch into which the data is to be entered is held
on the A, B and C inputs.
When ENABLE is taken low the data flows
through to the address output. The data is stored
on the positive-going edge of the ENABLE pulse.
All unadressed latches will remain unaffected.
With ENABLE in the high state the device is
deselected and all
latches remain in
previous state, unaffected by changes
their
on the
data
possibility of entering erroneous data into the
latches, the ENABLE should be held high
(inactive) while the address lines are changing. If
ENABLE is held high and CLEAR is taken low all
eight latches are cleared to the HIGH (OFF)
state. If ENABLE is low all latches except the
addressed latch will be cleared. The address
latch will instead be the complement of the D
input,effectively implementing a 3 to 8 line
decoder. Internal clamp diodes protect the open
drain outputs against over voltages due to
inductiveloads.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
or
address inputs.
To
eliminate
the
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
DIP
ORDER CODES
TUBE
PACKAGE
T & R
DIP
SOP
M74HCT7259B1R
M74HCT7259M1R M74HCT7259M1RTR
1/11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M74HCT7259M1R | 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT |
| M74HCT7259M1RTR | 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT |
| M74HCT74RM13TR | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR |
| M74HCT74-1 | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR |
| M74HCT74B1R | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M74HCT7259M1R | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 8-Bit Address Latch RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| M74HCT7259RM13TR | 制造商:STMicroelectronics 功能描述:LATCH/DECODER/DRVR SGL 3-TO-8 16SOIC - Tape and Reel |
| M74HCT74B1 | 制造商:STMicroelectronics 功能描述:Flip Flop, Dual, D Type, 14 Pin, Plastic, DIP |
| M74HCT74B1R | 功能描述:觸發(fā)器 Dual "D" Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| M74HCT74M1R | 功能描述:觸發(fā)器 Dual "D" Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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