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參數(shù)資料
| 型號(hào)： | M7A3P400-FG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁(yè)數(shù)： | 208/246頁(yè) |
| 文件大小： | 3010K |
| 代理商： | M7A3P400-FG484 |
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ProASIC3/E Flash Family FPGAs
2- 52
v2.1
Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O
logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O
banks.
Within
the
package,
the
GNDQ
plane
is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package, and
improves input signal integrity. GNDQ must always be
connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is
required for powering the JTAG state machine in
addition to VJTAG. Even when a ProASIC3 device is in
bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG
signals to pass through the ProASIC3 device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are eight I/O
banks on ProASIC3 devices plus a dedicated VJTAG bank.
Each bank can have a separate VCCI connection. All I/Os
in a bank will run off the same VCCIBx supply. VCCI can be
1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VCCI pins tied to
GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. x is the bank number. Within the package, the
VMV
plane
is
decoupled
from
the
simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package and improves input signal integrity. Each bank
must have at least one VMV connection and no VMV
should be left unconnected. All I/Os in a bank run off the
same VMVx supply. VMV is used to provide a quiet supply
voltage to the input buffers of each I/O bank. VMVx can
be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VMV pins tied to
GND. VMV and VCCI should be at the same voltage within
a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0
to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLF
PLL Supply Voltage7
Supply voltage to analog PLL, nominally 1.5 V. If unused,
VCCPLF should be tied to either the power supply or GND.
Refer to the PLL application note for a complete board
solution for the PLL analog power supply and ground.
VCOMPLF
PLL Ground7
Ground to analog PLL power supplies. Unused VCOMPLF
pins should be connected to GND.
VJTAG
JTAG Supply Voltage
ProASIC3 devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). Isolating the JTAG power supply
in a separate I/O bank gives greater flexibility in supply
selection and simplifies power supply and PCB design. If
the JTAG interface is neither used nor planned for use,
the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be
powered for JTAG operation; VJTAG alone is insufficient. If
a ProASIC3device is in a JTAG chain of interconnected
boards, the board containing the ProASIC3 device can be
powered down, provided both VJTAG and VCC to the
ProASIC3 part remain powered; otherwise, JTAG signals
will not be able to transition the ProASIC3 device, even
in bypass mode.
VPUMP
Programming Supply Voltage
ProASIC3
devices
support
single-voltage
ISP
programming of the configuration Flash and FlashROM.
For programming, VPUMP should be 3.3 V nominal.
During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage
between 0 V and 3.6 V. Programming power supply
voltage (VPP) range is 3.3 V +/- 5%.
When the VPUMP pin is tied to ground, it will shut off the
charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 F and 0.33 F capacitors
(both rated at 16 V) are to be connected in parallel across
VPUMP and GND, and positioned as close to the FPGA pins
as possible.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly
pulled up to VCCI. With VCCI, VMV, and VCC supplies
continuously powered up, when the device transitions
7. The A3P030 device does not support this feature.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P400-FGG144I | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| M7A3P400-FGG144 | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| M7A3P400-FGG256I | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| M7A3P400-FGG256 | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| M7A3P400-FGG484I | FPGA, 400000 GATES, 350 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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