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參數(shù)資料
| 型號： | M7A3P400-FGG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-144 |
| 文件頁數(shù)： | 191/246頁 |
| 文件大小： | 3010K |
| 代理商： | M7A3P400-FGG144 |
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ProASIC3/E Flash Family FPGAs
v2.1
2-37
For boards and cards with three levels of staging, card
power supplies must have time to reach their final value
before the I/Os are connected. Pay attention to the sizing
of power supply decoupling capacitors on the card to
ensure that the power supplies are not overloaded with
capacitance.
Cards with three levels of staging should have the
following sequence:
Grounds
Powers
I/Os and other pins
For Level 3 and Level 4 compliance with the A3P030
device, cards with two levels of staging should have the
following sequence:
Grounds
Powers, I/Os, and other pins
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
The A3P030 device fully supports cold-sparing, since the I/O
clamp diode is always off (see Table 2-13 on page 2-31).
For other ProASIC3 devices, since the I/O clamp diode is
always active, cold-sparing can be accomplished either by
employing a bus switch to isolate the device I/Os from the
rest of the system or by driving each ProASIC3 I/O pin to
0V.
If the A3P030 is used in applications requiring cold-
sparing, a discharge path from the power supply to
ground should be provided. This can be done with a
discharge resistor or a switched resistor. This is necessary
because the A3P030 does not have built-in I/O clamp
diodes.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitor is
in parallel with the resistor). The RC time constant should
ensure full discharge of supplies before cold-sparing
functionality is required. The resistor is necessary to
ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
Electrostatic Discharge (ESD) Protection
ProASIC3 devices are tested per JEDEC Standard
JESD22-A114-B.
ProASIC3 devices contain clamp diodes at every I/O,
global, and power pad. Clamp diodes protect all device
pads against damage from ESD as well as from excessive
voltage transients.
ProASIC3 devices are tested to the following models: the
Human Body Model (HBM) with a tolerance of 2,000 V,
the Machine Model (MM) with a tolerance of 250 V, and
the Charged Device Model (CDM) with a tolerance of
200 V.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND and its N side connected to the
pad. During operation, these diodes are normally
biased in the off state, except when transient voltage is
significantly above VCCI or below GND levels.
In A3P030, the first diode is always off. On other
ProASIC3 devices, the clamp diode is always on and
cannot be switched off.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-17 on page 2-38 for
more information about the I/O standards and the clamp
diode.
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
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