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參數(shù)資料
| 型號： | M902-01I187.5000 |
| 英文描述： | VCSO BASED GBE CLOCK GENERATOR |
| 中文描述： | 銀杏葉提取物才能開發(fā)出復(fù)雜基于時鐘發(fā)生器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 328K |
| 代理商： | M902-01I187.5000 |
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M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
F
UNCTIONAL
D
ESCRIPTION
The M902-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M902-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal or a stable external clock source such as a
packaged (temperature-compensated) crystal
oscillator.
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the
XTAL_1 / REF_IN
and
XTAL_2
input
pins. External crystal load trim capacitors are also
required. (See “Crystal Specifications” on pg. 4.)
If an external LVCMOS/LVTTL clock source is used,
apply it to the
XTAL_1 / REF_IN
input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M902-01 includes a
reference divider
that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The
EX_CLK
pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 3.
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output.
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
For the
M902-01-156.2500
(see “Ordering Information” on pg. 8):
VCSO output frequency = 156.25MHz
Input reference frequency = 25MHz
M=25
R= 4
Therefore, for the
M902-01-156.2500
:
4
156.25MHz = 25MHz
The product of the input crystal frequency and
falls within the lock range of the VCSO.
External Clock Feed-through
The
EXT_CLK
pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. This pin is intended for system debugging
and performance evaluation..
STOP Clock
The
STOP
pin puts the output clock into a static condition.
EN_EXT_CLK
Logic
1
enables the
EXT_CLK
input.
Use Logic
0
for normal operation.
EXT_CLK
Apply an external LVCMOS/LVTTL clock source
for
0
to
200
MHz feed-through operation.
Leave inactive for normal operation.
1
Note 1: In applications where EXT_CLK is active while the SAW PLL
signal path is enabled, it is necessary to gate the EXT_CLK to
minimize jitter in the LVPECL output pairs. See the
PCB Design
Guidelines for ICS SAW PLLs
application note at
www.icst.com/products/appnotes/M000-AN-001.PCBdesign.pdf
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
Fvcso
Fxtal
R
×
=
---------
×
R
M
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