參數(shù)資料
型號: M93S56-DW3TG
廠商: 意法半導(dǎo)體
英文描述: Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit 16位寬MICROWIRE串行EEPROM的訪問與街區(qū)保護(hù)
文件頁數(shù): 13/34頁
文件大?。?/td> 525K
代理商: M93S56-DW3TG
13/34
M93S66, M93S56, M93S46
Figure 7. PRCLEAR and PRDS Sequences
Note: For the meanings of An, Xn and Dn, please see
Table 2.
and
Table 3.
.
AI00892C
S
Protect
Register
CLEAR
1 1
D
Q
OP
CODE
1
BUSY
READY
CHECK
STATUS
ADDR
PRE
W
1 1 1
S
Protect
Register
DISABLE
1 0
D
Q
OP
CODE
0
BUSY
READY
CHECK
STATUS
ADDR
PRE
W
0 0 0
相關(guān)PDF資料
PDF描述
M93S56-DW3T 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection
M93S56-DW3P Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
M93S56-DW3G Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
M93S56-DW3 Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
M93S56-DS6TP Quadruple 2-Input Positive-NAND Gates 14-SO -40 to 85
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