參數(shù)資料
型號: M93S56-DW3TG
廠商: 意法半導(dǎo)體
英文描述: Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit 16位寬MICROWIRE串行EEPROM的訪問與街區(qū)保護(hù)
文件頁數(shù): 31/34頁
文件大小: 525K
代理商: M93S56-DW3TG
31/34
M93S66, M93S56, M93S46
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
Note: Drawing is not to scale.
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Symbol
mm
inches
Typ.
Min.
Max.
Typ.
Min.
Max.
A
1.200
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
1.000
0.800
1.050
0.0394
0.0315
0.0413
b
0.190
0.300
0.0075
0.0118
c
0.090
0.200
0.0035
0.0079
CP
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
0.0256
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0.0394
α
TSSOP8AM
1
8
CP
c
L
E
E1
D
A2
A
α
e
b
4
5
A1
L1
相關(guān)PDF資料
PDF描述
M93S56-DW3T 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection
M93S56-DW3P Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
M93S56-DW3G Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
M93S56-DW3 Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
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