參數(shù)資料
型號: M95080-R
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
中文描述: 16千位和8千位串行SPI高速時鐘總線的EEPROM
文件頁數(shù): 13/45頁
文件大?。?/td> 270K
代理商: M95080-R
M95160, M95080
Operating features
13/45
4.1.4
Power-down
At Power-down (continuous decrease of V
CC
), as soon as V
CC
drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on V
CC
.
4.2
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes I
CC
, as specified in
Table 13.
to
Table 18.
When Chip Select (S) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
CC1
.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low.
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
4.4
Status Register
Figure 6.
shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
Section 6.3: Read Status Register (RDSR)
for a
detailed description of the Status Register bits
相關(guān)PDF資料
PDF描述
M95080-W 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
M95160-R 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
M95160-W 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
M95128-MN6TPV 128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-DW3GP 128 Kbit Serial SPI bus EEPROM with high speed clock
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