參數(shù)資料
型號(hào): M95128-DW3GP
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 128 Kbit Serial SPI bus EEPROM with high speed clock
中文描述: 128千位的SPI高速時(shí)鐘總線的EEPROM
文件頁(yè)數(shù): 22/41頁(yè)
文件大?。?/td> 207K
代理商: M95128-DW3GP
Instructions
M95128, M95128-W, M95128-R
22/41
Figure 11.
Page Write (WRITE) sequence
1.
The most significant address bits (b15, b14) are Don’t Care.
5.6.1
ECC (Error Correction Code) and Write cycling
The M95128 (5V version, processed in F6DP26%, identified with letter "V") offers an ECC
(Error Correction Code) logic which compares each 4-Byte packet with its associated ECC
Word (6 EEPROM bits). As a result, if a single bit out of 4 Bytes of data happens to be
erroneous during a Read operation, the ECC detects it and replaces it by the correct value.
The read reliability is therefore much improved by the use of this feature.
Note however that even though a single Byte has to be written, 4 Bytes are internally
modified (plus the ECC Word), that is, the addressed Byte is cycled together with the three
other Bytes making up the packet. It is therefore recommended to Write by packets of 4
Bytes in order to benefit from the larger amount of Write cycles.
The maximum number of Write cycles for the M95128 device (5V version, processed in
F6DP26%, identified with letter "V") is qualified as 100,000 Write cycles, using a cycling
routine that writes to the device Page by Page (that is, by multiples of 4-Byte packets).
The M95128-W and M95128-R devices (2.5V and 1.8V versions, processed in F6DP36%
and identified with the letter "A") do not offer the ECC logic and are qualified for a maximum
number of 100,000 Write cycles.
C
D
AI01796D
S
34
33
35 36 37 38 39 40 41 42
44 45 46 47
32
C
D
S
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
Instruction
16-Bit Address
0
7
6
5
4
3
2
0
1
Data Byte 1
31
43
7
6
5
4
3
2
0
1
Data Byte 2
7
6
5
4
3
2
0
1
Data Byte 3
6
5
4
3
2
0
1
Data Byte N
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