參數(shù)資料
型號: M95128-MN6TV
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 128 Kbit Serial SPI bus EEPROM with high speed clock
中文描述: 128千位的SPI高速時鐘總線的EEPROM
文件頁數(shù): 20/41頁
文件大?。?/td> 207K
代理商: M95128-MN6TV
Instructions
M95128, M95128-W, M95128-R
20/41
5.5
Read from Memory Array (READ)
As shown in
Figure 9
, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 9.
Read from Memory Array (READ) sequence
1.
The most significant address bits (b15, b14) are Don’t Care.
C
D
AI01793D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
7
6
5
4
3
1
7
0
High Impedance
Data Out 1
Instruction
16-Bit Address
0
MSB
MSB
2
31
Data Out 2
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