參數(shù)資料
型號(hào): M95160-W
廠(chǎng)商: 意法半導(dǎo)體
元件分類(lèi): DRAM
英文描述: 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
中文描述: 16千位和8千位串行SPI高速時(shí)鐘總線(xiàn)的EEPROM
文件頁(yè)數(shù): 12/45頁(yè)
文件大?。?/td> 270K
代理商: M95160-W
Operating features
M95160, M95080
12/45
4
Operating features
4.1
Supply voltage (V
CC
)
4.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage
within the specified [V
CC
(min), V
CC
(max)] range must be applied (see
Table 9
,
Table 10
and
Table 11
). In order to secure a stable dc supply voltage, it is recommended to decouple the
V
CC
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
V
CC
/V
SS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t
W
).
4.1.2
Power-up conditions
When the power supply is turned on, V
CC
rises from V
SS
to V
CC
. During this time, the Chip
Select (S) line is not allowed to float but should follow the V
CC
voltage, it is therefore
recommended to connect the S line to V
CC
via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The V
CC
rise time must not vary faster than 1 V/μs.
4.1.3
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V
CC
), the device does not respond to any
instruction until V
CC
has reached the power on reset threshold voltage (this threshold is
lower than the minimum V
CC
operating voltage defined in
Table 9
,
Table 10
and
Table 11
).
Once V
CC
has passed the POR threshold, the device is reset and is in the following state:
Standby Power mode
deselected (at next power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
not in the Hold condition
Status Register state:
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are unchanged from the previous power-down (they are non-volatile bits).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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