參數(shù)資料
型號(hào)： M95256-WDW3T/A
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 32K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝： 0.169 INCH, TSSOP-8
文件頁數(shù)： 10/43頁
文件大?。?/td> 431K
代理商： M95256-WDW3T/A
Instructions
M95256, M95256-W, M95256-R
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Table 5.
Protection Modes
W Signal
SRWD
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area(1)
1.
As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
Unprotected Area(1)
10
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Write Protected
Ready to accept Write
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write
protected
The values in the BP1
and BP0 bits cannot be
changed
Write Protected
Ready to accept Write
instructions
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