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參數(shù)資料
| 型號(hào)： | MA31755 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| 中文描述： | 16位穿心錯(cuò)誤檢測(cè) |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 134K |
| 代理商： | MA31755 |
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MA31755
4/13
2.3.3 Correction
With no syndrome bits set data will pass through from the
MD bus to the PD bus unchanged. When a single bit error
occurs in the memory data word, MD[0:15], the three
syndrome bits which are set identify which data bit is in error.
The correction logic decodes these syndrome bits and will
correct the error provided the correction enable input, ENCOR,
is high.
2.3.4 Flag Generation
The correctable error flag,CERRN, is driven low whenever
1 or 3 syndrome bits are set and flags are enabled (ENFLG=1).
The non-correctable error flag, NCERRN, is driven low
whenever 2, 4, 5 or 6 Syndrome bits are set and flags are
again enabled (ENFLG=1). NCERRN will also be driven low
should the external error input, XERRN, be driven low at any
time. Note: this external error feedthrough from XERRN to
NCERRN operates independently of ENFLG and the Chip
Select inputs (CS0, CS1N & CS2N).
Flags are enabled provided the ENFLG input is high and
the device is selected. Note: the flags are not disabled on write
cycles and therefore can indicate errors on write operations
caused by faults on the Memory Data Bus and the Check Bit
Bus.
2.3.5 Internal Structure
Figure 5 below shows the internal block diagram
representing the internal architecture of the MA31755.
Figure 5: Block Diagram of the Internal Architecture of the MA31755
Check bit
generation
Tri-statable
Buffer
Tri-statable
Buffer
Correction
Syndrome
Generation
MD[0:16]
CB[0:5]
CERRN
NCERRN
PD[0:16]
ENCOR
ENFLG
XERRN
RDWN
CS0
CS1N
CS2N
Buffer
Control
Flags
Generation
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