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參數(shù)資料
| 型號： | MAC7121VVF |
| 廠商： | Motorola, Inc. |
| 英文描述： | MAC7100 Microcontroller Family Hardware Specifications |
| 中文描述： | MAC7100微控制器系列硬件規(guī)格 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 1514K |
| 代理商： | MAC7121VVF |
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18
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical Characteristics
3.8.6
Startup
Table 21 summarizes several startup characteristics explained in this section. Refer to the
MAC7100
Microcontroller Family Reference Manual
(MAC7100RM/D) for a detailed description of the startup
behavior.
3.8.6.1
Power On and Low Voltage Reset (POR and LVR)
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
2.5 supply. The assert level
V
LVRA
is derived from the V
DD
2.5 supply. They are also valid if the device is powered externally. After
releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup
time possible is given by t
uposc
(refer to Table 17).
3.8.6.2
SRAM Data Retention
The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a
reset operation.
3.8.6.3
External Reset
When external reset is asserted for a time greater than PW
RSTL
, the CRG module generates an internal reset
and the CPU starts fetching the reset vector without doing a clock quality check, if there was stable
oscillation before reset.
3.8.6.4
Stop Recovery
The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check
is performed in the same manner as for POR before releasing the clocks to the system.
3.8.6.5
Pseudo Stop and Doze Recovery
Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in
either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events
in the system. After t
wrs
, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or
continues to execute code if the wakeup event was not an interrupt.
Table 21. CRG Startup Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
K1
T POR release level
V
PORR
V
PORA
PW
RSTL
n
RST
PW
IRQ
t
WRS
—
—
2.07
V
K2
T POR assert level
0.97
—
—
V
K3
D Reset input pulse width, minimum input time
2
—
—
t
osc
n
osc
ns
K4
D Startup from Reset
192
—
196
K5
D Interrupt pulse width, IRQ edge-sensitive mode
20
—
—
K6
D Wait recovery startup time
—
—
14
t
cyc
F
Freescale Semiconductor, Inc.
n
.
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