參數(shù)資料
型號(hào)： MACH111SP-7VC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 22/48頁(yè)
文件大?。?/td> 1136K
代理商： MACH111SP-7VC
MACH 1 & 2 Families
29
MACH221 and MACH221SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
Parameter
Symbol
Parameter Description
-7
-10
-12
-14
-15
-18
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output
7.5
10
12
14
15
18
ns
ts
Setup Time from Input, I/O, or Feedback to
Clock
D-type
5.5
6.5
7
8.5
10
12
ns
T-type
6.5
7.5
8
10
11
13.5
ns
tH
Register Data Hold Time
000000
ns
tCO
Clock to Output
5
6
8
10
12
ns
tWL
Clock Width
LOW
35666
7.5
ns
tWH
HIGH
35666
7.5
ns
fMAX
Maximum
Frequency
External
Feedback
1/(tS + tCO)
D-type
95
80
66.7
54
50
42
MHz
T-type
87
74
62.5
50
47.6
39
MHz
Internal Feedback (fCNT)
D-type
133
100
83.3
69
66.6
55.6
MHz
T-type
125
91
76.9
62.5
51.3
MHz
No Feedback 1/(tWL + tWH)
167
100
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
000000
ns
tGO
Gate to Output
7
(note 2)
10
11
13.5
ns
tGWL
Gate Width LOW
35666
7.5
ns
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
9.5
12
14
17
20.5
ns
tSIR
Input Register Setup Time
22222
2.5
ns
tHIR
Input Register Hold Time
2
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
11
13
15
18
22
ns
tICS
Input Register Clock to Output Register Setup
D-type
9
10
12
14.5
15
18
ns
T-type
10
11
13
16
19.5
ns
tWICL
Input Register
LOW
35666
7.5
ns
tWICH
Clock Width
HIGH
35666
7.5
ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
167
100
83.3
66.7
MHz
tSIL
Input Latch Setup Time
22222
2.5
ns
tHIL
Input Latch Hold Time
2
2.5
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
14
17
20
24
ns
tIGOL
Input Latch Gate to Output Through Transparent Output
Latch
14
16
19
22
26.5
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
10
11
13
16
19.5
ns
tWIGL
Input Latch Gate Width LOW
35666
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
11.5
14
16
19
23
ns
tAR
Asynchronous Reset to Registered or Latched Output
9.5
15
16
19.5
20
24
ns
tARW
Asynchronous Reset Width (Note 3)
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
5
8
10
12
ns
tAP
Asynchronous Preset to Registered or Latched Output
9.5
15
16
19.5
20
24
ns
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