參數(shù)資料
型號(hào)： MACH131SP-12YI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： EE PLD, 10 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 34/48頁(yè)
文件大?。?/td> 1136K
代理商： MACH131SP-12YI
4
MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed xed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
14051K-002
Figure 1. Overall Architecture of MACH 1 & 2 Devices
Array and
Allocator
Output
Macrocells
Buried
Macrocells
I/O Cells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
Switch
Matrix
PAL Block
I/O Pins
PAL Block
Clock/Input Pins
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Block
Device
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
MACH111(SP)
21616
70
MACH131(SP)
41616
70
MACH211(SP)
416
8
68
MACH221(SP)
812
6
52
MACH231(SP)
816
8
68
(note 1)
I/O Pins
相關(guān)PDF資料
PDF描述
MACH131SP-14YI High-Performance EE CMOS Programmable Logic
MACH131SP-15VC High-Performance EE CMOS Programmable Logic
MACH131SP-5VC High-Performance EE CMOS Programmable Logic
MACH131SP-7VC High-Performance EE CMOS Programmable Logic
MACH131SP-7YI High-Performance EE CMOS Programmable Logic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MACH131SP-14YI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
MACH131SP-15VC 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述:
MACH131SP-15YC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic
MACH131SP-18YI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
MACH131SP-5VC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic
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