- 您現在的位置：買賣IC網 > PDF目錄180472 > MACH215-12JC (LATTICE SEMICONDUCTOR CORP) High-Density EE CMOS Programmable Logic PDF資料下載
參數資料
| 型號： | MACH215-12JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 8/30頁 |
| 文件大小： | 245K |
| 代理商： | MACH215-12JC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
16
MACH215-14/18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT= 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
14.5
18
24
ns
(Note 3)
D-type
6
7.5
10
ns
T-type
7.5
8.5
11
ns
tHA
Register Data Hold Time Using Product Term Clock
6
7.5
10
ns
tCOA
Product Term Clock to Output (Note 3)
17
22
26.5
ns
tWLA
LOW
10
11
15
ns
tWHA
HIGH
10
11
15
ns
D-type
42
33
26.5
MHz
T-type
40
32
25.5
MHz
D-type
47
36
28.5
MHz
T-type
44
34.5
27.5
MHz
50
44.5
33
MHz
D-type
8.5
12
16
ns
T-type
10
13.5
17
ns
tHS
Register Data Hold Time Using Global Clock
0
ns
tCOS
Global Clock to Output (Note 3)
10
12
14.5
ns
tWLS
LOW
7.5
10
ns
tWHS
HIGH
7.5
10
ns
D-type
53
40
32
MHz
T-type
50
38
30.5
MHz
fMAXS
D-type
66.5
53
40
MHz
T-type
61.5
50
38
MHz
66.5
50
MHz
tSLA
6
7.5
10
ns
tHLA
Latch Data Hold Time Using Product Term Clock
6
7.5
10
ns
tGOA
Product Term Gate to Output (Note 3)
19.5
23
26.5
ns
tGWA
Product Term Gate Width LOW (for LOW transparent)
10
11
14.5
ns
or HIGH (for HIGH transparent)
tSLS
Setup Time from Input, I/O, or Feedback to Global Gate
8.5
12
16
ns
tHLS
Latch Data Hold Time Using Global Gate
0
ns
tGOS
Gate to Output (Note 3)
12
13.5
14.5
ns
tGWS
Global Gate Width LOW (for LOW transparent)
7.5
10
ns
or HIGH (for HIGH transparent)
Maximum
Frequency
Using
Product
Term
Clock
(Note 1)
External Feedback
1/(tSA + tCOA)
Internal Feedback (fCNTA)
No Feedback
1/(tWLA+ tWHA)
Global Clock Width
-14
Maximum
Frequency
Using
Global
Clock
(Note 1)
Setup Time from Input, I/O, or
Feedback to Product Term Clock
External Feedback
1/(tSS + tCOS)
Internal Feedback (fCNTS)
No Feedback
1/(tWLS+ tWHS)
-18
-24
tSS
tSA
Setup Time from Input, I/O,
or Feedback to Global Clock
Setup Time from Input, I/O,
or Feedback to Product Term Gate
fMAXS
Product Term, Clock Width
相關PDF資料 |
PDF描述 |
|---|---|
| MACH215-15JC | High-Density EE CMOS Programmable Logic |
| MACH215-12 | High-Density EE CMOS Programmable Logic |
| MACH221SP-12YC | High-Performance EE CMOS Programmable Logic |
| MACH221SP-15YC | SUR ABSORBER 7MM 430V 1250A ZNR |
| MACH221SP-7YC | High-Performance EE CMOS Programmable Logic |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MACH21512JC14JI | 制造商:Advanced Micro Devices 功能描述: |
| MACH215-15JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21515JC18JI | 制造商:AMD 功能描述:NEW |
| MACH215-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH215-24JI | 制造商:Advanced Micro Devices 功能描述:EE PLD, 24 ns, PQCC44 |
發(fā)布緊急采購，3分鐘左右您將得到回復。