參數(shù)資料
型號(hào)： MACH215-15JC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Density EE CMOS Programmable Logic
中文描述： EE PLD, 15 ns, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 9/30頁(yè)
文件大?。?/td> 245K
代理商： MACH215-15JC
17
MACH215-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
tPDL
Input, I/O, or Feedback to Output Through
17
20.5
26.5
ns
Transparent Input or Output Latch
tSIR
Input Register Setup Time
2.4
ns
tHIR
Input Register Hold Time
3
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
18
22
28
ns
tICS
Input Register Clock to Output Register Setup
D-type
14.5
18
24
ns
T-type
16
19.5
25.5
ns
tWICL
LOW
7.5
10
ns
tWICH
HIGH
7.5
10
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL+ tWICH)
66.5
50
MHz
tSIL
Input Latch Setup Time
2.5
ns
tHIL
Input Latch Hold Time
3
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
20.5
24
30
ns
tIGOL
Input Latch Gate to Output Through Transparent
23
26.5
32.5
ns
Output Latch
Setup Time from Input, I/O, or Feedback Through
tSLLA
Transparent Input Latch to Product Term Output
8.5
10
12
ns
Latch Gate
tIGSA
Input Latch Gate to Output Latch Setup Using
8.5
10
12
ns
Product Term Output Latch Gate
tSLLS
Setup Time from Input, I/O, or Feedback Through
11
14.5
18
ns
Transparent Input Latch to Global Output Latch Gate
tIGSS
Input Latch Gate to Output Latch Setup Using Global
16
19.5
25.5
ns
Output Latch Gate
tWIGL
Input Latch Gate Width LOW
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
19.5
23
29
ns
Input and Output Latches
tAR
Asynchronous Reset to Registered or Latched Output
19.5
24
30
ns
tARW
Asynchronous Reset Width (Note 1)
14.5
18
24
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
10
12
18
ns
tAP
Asynchronous Preset to Registered or Latched Output
19.5
24
30
ns
tAPW
Asynchronous Preset Width (Note 1)
14.5
18
24
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
10
12
18
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
14.5
18
24
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
14.5
18
24
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be
used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous
clocks and tSA is the tS parameter for asynchronous clocks.
3. Parameters measured with 16 outputs switching.
-14
-18
-24
Input Register Clock Width
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