參數(shù)資料
型號： MAQ31753FXXXX
廠商： DYNEX SEMICONDUCTOR LTD
元件分類： DMA控制器
英文描述： 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
封裝： QFP-84
文件頁數(shù)： 15/31頁
文件大小： 238K
代理商： MAQ31753FXXXX
MA31753
22/31
Mil-Std-883, Method 5005, Subgroups 9, 10, 11.
TL = Low CLK period (ns), TH = High CLK period (ns).
Test Conditions: Vdd = 5.0V
±10%, Temperature = -55oC to 125oC, Vil = 0.0V, Vih = Vdd.
Output loads: All test load 1 unless otherwise specified.
Output Threshold: 50% Vdd (Load 1), Vss+1V, Vdd-1V (Load 2).
Note 1: A[0:15], AS[0:3], PS[0:3], PB[0:3], MION, OIN, RDWN, DMAKN, AS, DSN, RDN, WRN, LOCKN
Figure 15: Timing Parameters
No.
Description
Min
Max
Units
1
RESETN setup to CLK falling
-
ns
2
RESETN hold after CLK falling
-
ns
3
RESETN pulse wdth
-
ns
4
A[0:15] setup to CSN falling (DMA XIO)
-
ns
5
A[0:15] hold after DSN rising (DMA XIO)
-
ns
6
CSN setup to DSN falling (DMA XIO)
-
ns
7
CSN hold after DSN rising (DMA XIO)
-
ns
8
MION, OIN, RDWN setup to AS rising (DMA XIO)
-
ns
9
MION, OIN, RDWN hold after AS falling (DMA XIO)
-
ns
10
RDN falling to D[0:16] driven (XIO read)
ns
11
RDN falling to D[0:16] valid (XIO read)
ns
12
RDN rising to D[0:16] invalid (XIO read)
ns
13
RDN rising to D[0:16] tri-state (XIO read)
ns
14
D[0:16] setup to WRN rising (XIO write)
-
ns
15
D[0:16] hold after WRN rising (XIO write)
-
ns
16
CLK falling to RDYN valid (DMA XIO)
ns
17
CSN rising to RDYN tri-state (DMA XIO)
ns
18
CSN falling to RDYN driven (DMA XIO)
ns
19
CLK rising to AS rising
ns
20
CLK falling to AS falling
ns
21
A[0:15], AS[0:3], PS[0:3], PB[0:3] valid to AS rising
ns
22
A[0:15], AS[0:3], PS[0:3], PB[0:3] valid after AS falling
ns
23
MION, OIN, RDWN valid to DSN falling
ns
24
MION, OIN, RDWN valid after DSN rising
ns
25
CLK falling to AKRDN, AKWRN valid
ns
26
CLK falling to DACKN[0:3] falling
ns
27
CLK falling to DACKN[0:3] rising
ns
28
CLK falling to DMAKN valid
ns
29
CLK falling to DONEN valid
ns
30
CLK falling to DSN, RDN, WRN valid
ns
31
CLK falling to GEOUTN valid
ns
32
CLK falling to INTRN valid
ns
33
INTRN pulse width
ns
34
CLK falling to LOCKN falling
ns
35
CLK falling to LOCKN rising
ns
36
CLK falling to SEC/FIRSTN valid
ns
37
CLK falling to REQN valid
ns
38
DREQN[0:3] setup to CLK falling
-
ns
39
DREQN[0:3] hold after CLK falling
-
ns
40
EXADEN, MPROEN, PEN setup to AS falling
-
ns
41
EXADEN, MPROEN, PEN hold after AS faling
-
ns
42
GRANTN setup to CLK falling
-
ns
43
GRANTN hold after CLK falling
-
ns
44
GEINN setup to CLK falling
-
ns
45
GEINN hold after CLK falling
-
ns
46
RDYN setup to CLK falling
-
ns
47
RDYN hold after CLK falling
-
ns
48
REQINN setup to CLK falling
-
ns
49
REQINN hold after CLK falling
-
ns
50
CLK rising to busses, strobes and control signals (note 1) tri-state
ns
51
CLK falling to busses, strobes and control signals (note 1) driven
ns
52
D[0:16] setup to AKRDN rising
-
ns
53
D[0:16] hold after AKRDN rising
-
ns
54
D[0:16] valid after AKWRN falling
ns
55
D[0:16] valid after AKWRN rising
ns
56
DPARN setup to CLK falling
-
ns
57
DPARN hold after CLK falling
-
ns
58
DTON setup to CLK falling
-
ns
59
DTON hold after CLK falling
-
ns
60
DMAE setup to CLK falling
-
ns
61
DMAE hold after CLK falling
-
ns
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