參數(shù)資料
型號(hào): MAR28155LXXXX
廠商: DYNEX SEMICONDUCTOR LTD
元件分類: 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, CQCC44
封裝: LCC-44
文件頁(yè)數(shù): 15/20頁(yè)
文件大?。?/td> 254K
代理商: MAR28155LXXXX
MA28155
4/20
OPERATING MODE 0
(Basic Input/Output)
This functional configuration provides simple input and
output operation for each of the three ports. No handshaking is
required; data is simply written to or read from a specified port.
s Two 8-bit ports and 4-bit ports
s Any port can be input or output
s Outputs are latched
s Inputs are not latched.
s 16 different Input/Output configurations are possible in this
Mode.
Group A and Group B Controls
The functional configuration of each port is programmed by
the system software. In essence, the CPU outputs a control
word to the MA28155. The control word contains information
such as mode, bit set, bit reset, etc., this initializes the
functional configuration of the MA28155.
Each of the Control blocks (Group A and Group B) accept
commands from the Read/Write Control Logic, receive control
words from the internal data bus and issue the proper
commands to its associated ports:
Control Group A - Port A and Port C upper (C7-C4) Control
Group B - Port B and Port C lower (C3-C0)
The Control Word Register can only be written into.
Therefore reading of the Control Word Register is not allowed .
Ports A, B and C
The MA28155 contains three 8-bit ports (A, B, and C). All
can be configured in a wide variety of functional characteristics
by the system software but each has its own special features
to further enhance the power and flexibility of the MA28155.
Port A.
One 8-bit data output latch/buffer and one 8-bit data input
latch.
Port B.
One 8-bit data input/output latch/buffer and one 8-bit input
buffer
Port C.
One 8-bit data output latch/buffer and one 8-bit data input
buffer (no latch for input) This port can be divided into two 4-bit
ports under the mode control. Each 4-bit port contains a 4-bit
latch and it can be used for the control signal outputs and
status signal inputs in conjunction with ports A and B
Figure 5: Basic Input (Read) Timing Diagram
DSN
CSN, A1, A0
RD/WN
RD/WN set-up and hold time
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