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參數(shù)資料
| 型號： | MAR31753FXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84 |
| 封裝： | QFP-84 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大小： | 238K |
| 代理商： | MAR31753FXXXX |
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MA31753
2/31
1.0 GENERAL DESCRIPTION
The MA31753 DMA controller has 4 channels from which
independant transfers can be executed. These channels have
programmable priorities and can be masked. They can also be
enabled and disabled under software control.
The data can be transferred in several modes - single word
mode, double word mode and burst mode. It can be
transferred to and from both incrementing and decrementing
memory and IO addressing space. The single and double word
modes transfer data in 1 or 2 bus cycles when the simple
handshaking mechanism is enabled.
If more than 4 channels are required, several DMA
controllers can be cascaded together to give channel
expansion.
Once a channel has requested a transfer, and the bus
arbiter has granted bus control to the DMA, then the DMA
issues an acknowledge signal to the channel to be serviced. It
also pulses read or write strobes which can be gated with the
channel acknowledge signal to provide read and write strobes
for the requesting hardware.
DMA instructions can be programmed into memory on the
DMA. The transfers defined by these instructions can be
executed in sequence if they are “chained together”. In this
way, DMA transfers can take place continuously with data that
is held in seperate memory areas.
There is software access to all internal registers. These
registers have parity protection. By setting certain bits in
registers, requests can be initiated for area to area transfers on
channels 0 and 1. Interrupts for each channel can also be
issued.
2.0 INITIALISATION
After RESETN has been removed the DMA is
automatically initiated to be disabled with odd parity, the
channel priority order is 0, 1, 2, 3, C (C is the cascaded input)
and all channels are masked. At this point, before the DMA is
used further, the DMA instructions should be programmed into
the DMA internal RAM. Once all the instructions needed are in
place, the common features (ie. features that apply to all
channels) on the DMA can be programmed.These features
should be initialised to the users requirements.
The bus parity may be changed immediately after
RESETN goes inactive when the MA31750 reads the
configuration word ie. When the DMA detects the XIO address
0x8410, it snoops the data bus and latches the parity bit into an
internal copy. This internal copy can later be changed by
writing to the DMA Mode / Status register.
The DMA enable / disable follows the DMAE input - when
this input is high, the DMA device is enabled. When DMAE is
low, the DMA is disabled.
The channel priority and masking can be changed by
writing to the DMA Mode / Status register.
Once the common characteristics of the DMA have been
set up, the DMA individual channels can be programmed.
Each channel has a mode register that should be programmed
with an instruction number as that channel is activated (by
writing the mode word).
Figure 2: Block Diagram Representing the DMA Controller
Channel 1
Handler
Channel 2
Handler
Channel 3
Handler
Channel 4
Handler
PRIORITIZER
BUS MANAGER
BUS INTERFACE
DMA
req
DMA
ack
DMA
req
DMA
ack
DMA
req
DMA
ack
DMA
req
DMA
ack
DMARQN
A[0:15]
RD
WN
Doub
le
RD
YN
Cascaded
request
out (REQN)
Bus grantn
(GRANTN)
Grant enable
out (GEOUTN
Cascaded grant
enable in
(GEINN)
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| MAS31753FXXXX | 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84 |
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