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參數(shù)資料
| 型號： | MAX1247BMJE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16 |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16 |
| 封裝： | CERDIP-16 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 223K |
| 代理商： | MAX1247BMJE |
M
+2.7V, Low-Power, 4-Channel,
S erial 12-Bit ADCs in QS OP-16
______________________________________________________________________________________
17
Figure 12. Average Supply Current vs. Conversion Rate with
External Reference
1000
10,000
0.1
0.1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
WITH EXTERNAL REFERENCE
100
10
1
CONVERSION RATE (Hz)
D
1
100
10
1k
10k
1M
100k
M
V
REF
= V
DD
= 3.0V
R
=
∞
CODE = 101010100000
1 CHANNEL
4 CHANNELS
Figure 13b. MAX1246 Supply Current vs. Conversion Rate,
FASTPD
10,000
1
0.1
1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FASTPD)
1000
100
10
CONVERSION RATE
(Hz)
I
D
μ
A
100
1M
10
1k
10k
100k
M
R
LOAD
=
∞
CODE = 101010100000
4 CHANNELS
1 CHANNEL
Figure 13a. MAX1246 Supply Current vs. Conversion Rate,
FULLPD
100
1
0.01
0.1
1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FULLPD)
10
CONVERSION RATE
(Hz)
A
μ
A
100
10
1k
M
R
=
∞
CODE = 101010100000
4 CHANNELS
1 CHANNEL
Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
2.0
0.0
0.001
0.01
TIME IN SHUTDOWN
(sec)
0.1
1
10
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
1.5
1.0
0.5
P
M
Power-Down S equenc ing
The MAX1246/MAX1247 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 12, 13a, and 13b show
the average supply current as a function of the sam-
pling rate. The following discussion illustrates the vari-
ous power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 13a depicts the MAX1246 power consumption
for one or four channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.047μF bypass capacitor at REFADJ forms an RC filter
with the internal 20k
reference resistor with a 0.9ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 9ms are required after power-up. Waiting
this 9ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 14.
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