參數(shù)資料
型號: MAX127AEAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大小: 0K
描述: IC DAS 12BIT 2-WIRE 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 12 b
采樣率(每秒): 8k
數(shù)據(jù)接口: I²C,串行
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address.
The first four bits (MSBs) of the slave address have
been factory programmed and are always 0101. The
logic state of the address input pins (A2–A0) determine
the three LSBs of the device address (Figure 3). A max-
imum of eight MAX127/MAX128 devices can therefore
be connected on the same bus at one time.
A2–A0 may be connected to VDD or DGND, or they
may be actively driven by TTL or CMOS logic levels.
The eighth bit of the address byte determines whether
the master is writing to or reading from the MAX127/
MAX128 (R/W = 0 selects a write condition. R/W = 1
selects a read condition).
Conversion Control
The master signals the beginning of a transmission with
a START condition (S), which is a high-to-low transition
on SDA while SCL is high. When the master has fin-
ished communicating with the slave, the master issues
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 4). The bus is then
free for another transmission. Figure 5 shows the timing
diagram for signals on the 2-wire interface. The
address-byte, control-byte, and data-byte are transmit-
ted between the START and STOP conditions. The SDA
state is allowed to change only while SCL is low, except
for the START and STOP conditions. Data is transmitted
in 8-bit words. Nine clock cycles are required to trans-
fer the data in or out of the MAX127/MAX128. (Figures
9 and 10).
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
______________________________________________________________________________________
11
SCL
SDA
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS A2, A1, AND A0.
0
1
A2
1
R/W
A1
A0
LSB
ACK
SLAVE ADDRESS
Figure 3. Address Byte
SCL
SDA
tLOW
tHIGH
tF
tR
tHD, STA
tHD, DAT
tHD, STA
tSU, DAT
tSU, STA
tBUF
tSU, STO
START CONDITION
STOP CONDITION
REPEATED START CONDITION
START CONDITION
Figure 5. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
START CONDITION
STOP CONDITION
Figure 4. START and STOP Conditions
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