參數(shù)資料
型號(hào)： MAX1281BEUP+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/24頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 300KSPS 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 74
位數(shù)： 12
采樣率（每秒）： 300k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 559mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 1396 (CN2011-ZH PDF)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
11
Detailed Description
The MAX1280/MAX1281 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to microprocessors
(Ps). Figure 3 shows a functional diagram of the
MAX1280/MAX1281.
Pseudo-Differential Input
The equivalent input circuit of Figure 4 shows the
MAX1280/MAX1281’s input architecture, which is com-
posed of a T/H, input multiplexer, input comparator,
switched-capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 2 and 3.
The MAX1280/MAX1281 input configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) is connected to the sampling capacitor
while converting and must remain stable within ±0.5LSB
(±0.1LSB for best results) with respect to GND during a
conversion.
If a varying signal is applied to the selected IN-, its ampli-
tude and frequency must be limited to maintain accuracy.
The following equations determine the relationship
between the maximum signal amplitude and its frequency
in order to maintain ±0.5LSB accuracy. Assuming a sinu-
soidal signal at IN-, the input voltage is determined by:
The maximum voltage variation is determined by:
A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB
of error when using a +2.5V reference voltage and a
2.5s conversion time (15/fSCLK). When a DC reference
voltage is used at IN-, connect a 0.1F capacitor to
GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 12-bit
resolution. This action is equivalent to transferring a
12pF x (VIN+ - VIN-) charge from CHOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
max
d
-
d
- 2f
1LSB
t
V
2t
IN
t
IN
CONV
REF
12
CONV
ν
π
=
()
≤
=
V
νπ
IN
-- sin(2 ft)
=
()
V
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.22V
REFERENCE
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
IN
DOUT
SSTRB
VDD1
VDD2
GND
SCLK
DIN
COM
REFADJ
REF
OUT
REF
CLOCK
+2.500V
17k
10
9
12
11
14
15
16
17
18
CH6
7
CH7
8
CH4
5
CH5
6
CH1
2
CH2
3
CH3
4
CH0
1
MAX1280
MAX1281
CS
SHDN
20
19
13
≈ 2.05*
A
Figure 3. Functional Diagram
CHOLD
RIN
800
12pF
HOLD
INPUT
MUX
CSWITCH*
*INCLUDES ALL INPUT PARASITICS
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CH0
REF
GND
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ZERO
VDD1/2
COMPARATOR
CAPACITATIVE
DAC
6pF
TRACK
Figure 4. Equivalent Input Circuit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1281BEUP+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1281BEUP+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1281BEUP-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1282ACEE 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1282AEEE 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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