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參數(shù)資料
| 型號： | MAX1281BEUP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 300KSPS 20-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 74 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 300k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 559mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 1396 (CN2011-ZH PDF) |
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
16
______________________________________________________________________________________
progress. In software power-down mode, the serial
interface remains active, waiting for a new control byte
to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes
into the programmed power mode until a new control
byte is written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode or exiting hardware shutdown, the device goes
immediately into full-power mode and is ready to con-
vert after 2s when using an external reference. When
using the internal reference, wait for the typical power-
up delay from a full power-down (software or hard-
ware), as shown in Figure 9.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software shutdown is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-
quiescent-current state (2A, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1280/MAX1281 into their full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 =
1, a 0.9mA power-down starts after the conversion.
112
B11
B6
B0
B11
B6
B0
B11
B6
16
8
1
12
16
8
5
1
12
16
8
51
SETC
S
CONTROL BYTE 2
S
CONTROL BYTE 1
S
DIN
SCLK
DOUT
SSTRB
CS
CONTROL BYTE 0
CONVERSION RESULT 0
CONVERSION RESULT 1
5
HIGH-Z
Figure 8. Continuous 16-Clock/Conversion Timing
PD1/PD0
MODE
CONVERTING
AFTER
CONVERSION
INPUT COMPARATOR
REFERENCE
00
Full Power-Down
(FULLPD)
2.5mA
2A
Off
01
Fast Power-Down
(FASTPD)
2.5mA
0.9mA
Reduced Power
On
10
Reduced-Power
Mode (REDPD)
2.5mA
1.3mA
Reduced Power
On
11
Operating Mode
2.5mA
2.0mA
Full Power
On
CIRCUIT SECTIONS*
TOTAL SUPPLY CURRENT
Table 4. Software-Controlled Power Modes
*Circuit operation between conversions; during conversion, all circuits are fully powered up.
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