參數(shù)資料
型號: MAX1402CAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 22/38頁
文件大?。?/td> 0K
描述: IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 34mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 3 個差分,單極;3 個差分,雙極;5 個偽差分,單極;5 個偽差分,雙極
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
29
The noise shown in Table 16 is composed of device
noise and quantization noise. The device noise is rela-
tively low, but becomes the limiting noise source for
high gain settings. The quantization noise is dependent
on the notch frequency and becomes the dominant
noise source as the notch frequency is increased.
Offset-Correction DAC
The MAX1402 provides a coarse (3-bit plus sign) offset-
correction DAC at the modulator input. Use this DAC to
remove the offset component in the input signal, allow-
ing the ADC to operate on a more sensitive range. The
DAC offsets up to ±116.7% of the selected range in
±16.7% increments for unipolar mode and up to
±58.3% of the selected range in ±8.3% increments for
bipolar mode. When a DAC value of 0 is selected, the
DAC is completely disconnected from the modulator
inputs and does not contribute any noise. Figures 7
and 9 show the effect of the DAC codes on the input
range and transfer function.
Clock Oscillator
The clock oscillator may be used with an external crystal
(or resonator) connected between CLKIN and CLKOUT,
or may be driven directly by an external oscillator at
CLKIN with CLKOUT left unconnected. In normal oper-
ating mode, the MAX1402 is specified for operation with
CLKIN at either 1.024MHz (CLK = 0) or 2.4576MHz
(CLK = 1, default). When operated at these frequencies,
the part may be programmed to produce frequency
response nulls at the local line frequency (either 60Hz or
50Hz) and the associated line harmonics.
In standby mode (STBY = 1) all circuitry, with the
exception of the serial interface and the clock oscillator,
is powered down. The interface consumes minimal
power with a static SCLK. Enter power-down mode
(including the oscillator) by setting the FULLPD bit in
the special-function register. When exiting a full-power
shutdown, perform a hardware reset or a software reset
after the master clock signal is established (typically
10ms when using the on-board oscillator with an exter-
nal crystal) to ensure that any potentially corrupted reg-
isters are cleared.
It is often helpful to use higher-frequency crystals or
resonators, especially for surface-mount applications
where the result may be reduced PC board area for the
oscillator component and a lower price or better com-
ponent availability. Also, it may be necessary to oper-
ate the part with a clock source whose duty cycle is not
close to 50%. In either case, the MAX1402 can operate
with a master clock frequency of up to 5MHz, and
includes an internal divide-by-2 prescaler to restore the
internal clock frequency to a range of up to 2.5MHz
with a 50% duty cycle. To activate this prescaler, set
the X2CLK bit in the control registers. Note that using
CLKIN frequencies above 2.5MHz in combination with
the X2CLK mode will result in a small increase in digital
supply current.
Digital Filter
The on-chip digital filter processes the 1-bit data
stream from the modulator using a SINC3 or SINC1 fil-
ter. The SINC filters are conceptually simple, efficient,
and extremely flexible, especially where variable reso-
lution and data rates are required. Also, the filter notch
positions are easily controlled, since they are directly
related to the output data rate (1 / data word period).
The SINC1 function results in a faster settling response
while retaining the same frequency response notches
as the default SINC3 filter. This allows the filter to settle
faster at the expense of resolution and quantization
noise. The SINC1 filter settles in one data word period.
With 60Hz notches (60Hz data rate), the settling time
would be 1 / 60Hz or 16.7ms whereas the SINC3 filter
would settle in 3 / 60Hz or 50ms. Toggle between these
filter responses using the FAST bit in the global setup
register. Use SINC1 mode for faster settling and switch
to SINC3 mode when full accuracy is required. Switch from
the SINC1 to SINC3 mode by resetting the FAST bit low.
The DRDY signal will go false and will be reasserted
DAC CODE
D3:
D2:
D1:
D0:
INPUT
VOLTAGE
RANGE
(VREF = 2.5V
PGA = 000)
(VREF = 1.25V
PGA = 000)
-7
1
-6
1
0
-5
1
0
1
-4
1
0
-3
1
0
1
-2
1
0
1
0
-1
1
0
1
0
+1
0
1
+2
0
1
0
+3
0
1
+4
0
1
0
+5
0
1
0
1
+6
0
1
0
+7
0
1
2.708V
2.50V
2.292V
2.083V
1.875V
1.667V
1.458V
1.25V
1.042V
0.833V
0.625V
0.416V
0.208V
0V
-0.208V
-0.416V
-0.625V
-0.833V
-1.042V
-1.25V
-1.458V
-1.667V
-1.875V
-2.083V
-2.292V
-2.50V
-2.708V
13/6 VREF/2PGA
2 VREF/2PGA
11/6 VREF/2PGA
10/6 VREF/2PGA
9/6 VREF/2PGA
8/6 VREF/2PGA
7/6 VREF/2PGA
VREF/2PGA
5/6 VREF/2PGA
4/6 VREF/2PGA
3/6 VREF/2PGA
2/6 VREF/2PGA
1/6 VREF/2PGA
0
-1/6 VREF/2PGA
-2/6 VREF/2PGA
-3/6 VREF/2PGA
-4/6 VREF/2PGA
-5/6 VREF/2PGA
-VREF/2PGA
-7/6 VREF/2PGA
-8/6 VREF/2PGA
-9/6 VREF/2PGA
-10/6 VREF/2PGA
-11/6 VREF/2PGA
-2 VREF/2PGA
-13/6 VREF/2PGA
5.00V
4.503V
4.167V
3.750V
3.333V
2.917V
2.50V
2.083V
1.667V
1.25V
0.833V
0.416V
0V
-0.416V
-0.833V
-1.25V
-1.667V
-2.083V
-2.50V
-2.917V
-3.333V
-3.750V
-4.167V
-4.503V
-5.00V
MINIMUM
INPUT
(U/B
= 1)
MINIMUM
INPUT
(U/B
= 0)
MAXIMUM
INPUT
Figure 9. Input Voltage Range vs. DAC Code
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