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參數(shù)資料
| 型號： | MAX1402EAI+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 36/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT LP 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | MAX11200 ADC Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 46 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 480 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 34mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 1396 (CN2011-ZH PDF) |
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MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________
7
TIMING CHARACTERISTICS
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX,
unless otherwise noted.) (Notes 19, 20, 21)
0
100
VDD = 3.3V
VDD = 5V
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t10
10
100
ns
VDD = 5V
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t6
080
ns
INT High Time
tINT
560 / N
tCLKIN
ns
X2CLK = 1, N = 2(2 MF1 + MF0)
Crystal oscillator or clock exter-
nally supplied for specified perfor-
mance (Notes 22, 23)
SCLK Setup to Falling Edge CS
t4
30
ns
SCLK Low Pulse Width
t8
100
ns
10
70
SCLK Rising Edge to INT High
(Note 27)
t11
100
VDD = 5V
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 21)
t9
0
ns
SCLK High Pulse Width
t7
100
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t5
30
ns
280 / N
tCLKIN
INT to CS Setup Time (Note 8)
t3
X2CLK = 0, N = 2(2 MF1 + MF0)
0
ns
RESET Pulse Width Low
t2
100
ns
Master Clock Input Low Time
fCLKIN LO
0.4
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Input High Time
fCLKIN HI
0.4
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Frequency
fCLKIN
0.8
5.0
MHz
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
0.4
2.5
CONDITIONS
200
ns
X2CLK = 0
X2CLK = 1
VDD = 3.3V
Note 12: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-
tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
Note 13: VREF = VREFIN+ - VREFIN-.
Note 14: These specifications apply to CLKOUT only when driving a single CMOS load.
Note 15: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate cor-
rectly.
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
30
ns
t12
SCLK Setup to Falling Edge CS
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION
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