參數(shù)資料
型號(hào)： MAX1402EAI+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 37/38頁(yè)
文件大小： 0K
描述： IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊： MAX11200 ADC
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 46
位數(shù)： 18
采樣率（每秒）： 480
數(shù)據(jù)接口： QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 34mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 1396 (CN2011-ZH PDF)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8
_______________________________________________________________________________________
Note 19: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 20: See Figure 4.
Note 21: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1402 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23: The MAX1402 is production tested with fCLKIN at 2.5MHz (1MHz for some IDD tests).
Note 24: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
Note 25: For read operations, SCLK active edge is falling edge of SCLK.
Note 26: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 28: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
SCLK High Pulse Width
t16
100
ns
SCLK Low Pulse Width
t17
100
ns
Data Valid to SCLK Rising Edge
Hold Time
t15
0
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t13
30
ns
Data Valid to SCLK Rising Edge
Setup Time
t14
30
ns
CONDITIONS
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX,
unless otherwise noted.) (Notes 19, 20, 21)
CS Rising Edge to SCLK Rising
Edge Hold Time
t18
0
ns
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21 & 28)
t20
0
ns
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21 & 28)
t19
40
ns
800
A
at VDD = +5V
100
A
at VDD = +3.3V
TO
OUTPUT
PIN
50pF
200
A
at VDD = +5V
100
A
at VDD = +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and VOL and
VOH Levels
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1402EAI+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1402EAI+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1402EAI+TW 功能描述:ADC / DAC多通道 +5V 18-Bit Low-Power Multichannel Oversampling (Sigma-Delta) ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1402EAI+W 功能描述:ADC / DAC多通道 +5V 18-Bit Low-Power Multichannel Oversampling (Sigma-Delta) ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1402EAI-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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