參數(shù)資料
型號: MAX1464AAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/47頁
文件大?。?/td> 0K
描述: IC SENSOR SIGNAL COND 28-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
類型: 信號調(diào)節(jié)器
輸入類型: 模擬
輸出類型: 邏輯
接口: SPI
電流 - 電源: 890µA
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
24
Maxim Integrated
Description:
Perform a 16-bit shift-left operation on the contents of
X-register. The most significant bit, bit 15, is truncated
and lost. If register X is any CPU register other than
register R6, then a zero is appended into the LSB, bit 0.
If X is CPU register R6, then the data appended into the
LSB bit 0 is copied from the MSB of register R4. The
contents of register R4 are not affected. The operation
does not preserve the two’s-complement sign bit-15.
The operation is equivalent to an arithmetic multiplica-
tion by 2 on an unsigned integer value stored in regis-
ter X. The result is stored back into the X-register. The
previous contents of the X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
SRX
Shift Right Register X
Op-code: 0111 XXXXBINARY 7Xh
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 15-bit shift-right operation on the contents of
X-register, preserving the contents of the two’s-comple-
ment sign bit-15 and propagating the sign bit, bit-15,
into bit-14. The least significant bit, bit 0, is truncated
and lost. The operation is equivalent to an arithmetic
division by 2. The result is stored back into the X-regis-
ter. The previous contents of the X-register are overwrit-
ten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
INX
Increment Register X
Op-code:
1000 XXXXBINARY 8Xh
Operation:
X-register
← X-register + 1
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit increment operation on the contents of
the X-register. Should the increment result in an over-
flow, the overflow bit is truncated and lost. The result is
stored back into the X-register. The previous contents
of the X-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
DEX
Decrement Register X
Op-code:
1001 XXXXBINARY 9Xh
Operation:
X-register
← X-register - 1
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit decrement operation on the contents
of the X-register. Should the decrement result in an
underflow, the underflow bit is truncated and lost. The
result is stored back into the X-register. The previous
contents of the X-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
NGX
Negate Register X
Op-code:
1010 XXXXBINARY AXh
Operation:
X-register
← NOT X-register
14
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT:
REGISTER X
Operation
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