參數(shù)資料
型號: MAX14821EVKIT#
廠商: Maxim Integrated Products
文件頁數(shù): 6/31頁
文件大小: 0K
描述: EVAL KIT MAX14821
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,收發(fā)器
已用 IC / 零件: MAX14821
主要屬性: IO和SPI接口端子
次要屬性: 圖形用戶界面
已供物品: 板,線纜,軟件
MAX14821
IO-Link Device Transceiver
14
Maxim Integrated
Pin/Bump Configurations
Pin/Bump Descriptions
PIN
NAME
FUNCTION
TQFN-EP
WLP
1
A2
LDOIN
5V Linear Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.
2
A3
V5
5V Power-Supply Input and 5V Linear Regulator Output. Bypass V5 to GND with a 0.1FF
ceramic capacitor for 10mA load capability. Add the recommended compensation network
to increase the source capability to 30mA. See the 5V and 3.3V Linear Regulators section for
more information.
3
A4
LDO33
3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor.
4
B3
IRQ
Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL.
5
A5
SCLK
SPI Clock Input
6
B4
CS
Active-Low SPI Chip-Select Input
7
B5
SDO
SPI Serial-Data Output
8
C4
SDI
SPI Serial-Data Input
9
C5
VL
Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs.
Bypass VL to GND with a 0.1FF ceramic capacitor.
10
C3
I.C.
Internally Connected. Connect to VL or leave unconnected.
23
24
22
21
8
7
9
V 5
IRQ
SCLK
CS
10
LDOIN
LI
WU
RX
UV
TXEN
12
DO
45
6
17
18
16
14
13
VCC
VP
I.C.
VL
SDI
SDO
*EP
*CONNECT EXPOSED PAD TO GND.
LDO33
LO
3
15
C/Q
20
11 TXQ
GND
19
12 TXC
DI
TQFN
TOP VIEW
+
MAX14821
TOP VIEW
(BUMP SIDE DOWN)
A
B
C
D
WLP
E
1234
VCC
LDOIN
V5
LDO33
SCLK
C/Q
VP
IRQ
SDO
GND
I.C.
SDI
VL
DO
UV
TXC
TXQ
DI
LI
LO
RX
TXEN
5
+
CS
WU
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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