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參數(shù)資料
| 型號： | MAX148 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | +2.7V至+5.25V、低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | MAX148 |
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
12
______________________________________________________________________________________
remaining bits in MSB-first format (Figure 9).
CS
does
not need to be held low once a conversion is started.
Pulling
CS
high prevents data from being clocked into
the MAX148 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when
CS
goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148 at clock rates exceeding 2.0MHz, provid-
ed that the minimum acquisition time, t
ACQ
, is kept
above 1.5μs.
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START
SEL2 SEL1 SEL0BIP
DIF
PD1 PD0
B9
B8
B7
B0
S1
S0
ACQUISITION
(CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5μs MAX
(SHDN = FLOAT)
A/D STATE
2
3
5
6
7
9
10
11
19
21
22
23
t
CONV
1.5μs
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
DOUT
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
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