MAX1549
Digital Soft-Start
Soft-start allows a gradual increase of the internal cur-
rent-limit level during startup to reduce the input surge
currents. Both controllers contain an internal digital
soft-start circuit. In shutdown mode or input UVLO, the
controller resets the soft-start counter to zero.
The MAX1549 divides the soft-start period into five
phases. During the first phase, the controller limits the
peak current limit to only 20% of the full current limit. If
the output does not reach regulation within 128 clock
cycles (1 / fOSC), soft-start enters the second phase
and increments the current limit by another 20%. This
process repeats until soft-start reaches the maximum
current limit after 512 clock cycles or until the output
reaches the nominal regulation voltage, whichever
occurs first (see the Soft-Start Waveforms in the Typical
Operating Characteristics). The exact rise time of the
output voltage depends on the output capacitance and
load current.
Soft-Shutdown
Soft-shutdown slowly discharges the output capaci-
tance, providing a damped shutdown response. This
eliminates the slightly negative output voltages caused
by quickly discharging the output through the inductor
and low-side MOSFET. Both controllers contain sepa-
rate soft-shutdown circuits.
When the controller is disabled—ON_ pulled low, the
UV fault latch set, or input UVLO triggered—the
MAX1549 discharges the respective output through an
internal 12
switch to ground. While the output dis-
charges, the MAX1549 forces DL_ low and disables the
PWM controller, but the reference remains active to
provide an accurate threshold. Once the output voltage
drops below 0.3V, the MAX1549 pulls DL_ high, effec-
tively clamping the output and LX_ switching node to
ground. The reference shuts down once both outputs
are disabled and discharged below 0.3V.
Power-Good Output (PGOOD_)
The MAX1549 includes separate open-drain outputs for
the power-good window comparators (Figure 7) that
monitor each output continuously (except during main-
output fault blanking; see the Fault and Power-Good
Blanking section). The controller actively holds
PGOOD_ low in shutdown and during soft-start. Once
the digital soft-start terminates, PGOOD_ becomes high
impedance as long as the respective output voltage is
within
±10% of the nominal regulation voltage. When
either output voltage drops 10% below or rises 10%
above the nominal regulation voltage, the MAX1549
pulls the respective PGOOD_ output low. Any fault con-
dition forces both PGOOD1 and PGOOD2 low until the
fault latch is cleared by toggling ON1 or ON2, or
cycling VCC power below 1V. For logic-level output volt-
ages, connect an external pullup resistor between
PGOOD_ and VCC. A 100k
resistor works well in most
applications.
The power-good window comparators are completely
independent of the overvoltage and undervoltage-pro-
tection fault comparators.
Fault Protection
Overvoltage Protection (OVP)
If either output voltage rises above 114.5% of its nomi-
nal regulation voltage, the OVP circuit sets the fault
latch, pulls PGOOD1 and PGOOD2 low, shuts down
both PWM controllers, and immediately pulls DH_ low
and forces DL_ high. This turns on the synchronous-
rectifier MOSFETs with 100% duty, rapidly discharging
the output capacitors and clamping both outputs to
ground. However, immediately latching DL_ high typi-
cally causes slightly negative output voltages due to
Dual, Interleaved, Fixed-Frequency Step-Down
Controller with a Dynamically Adjustable Output
24
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MAX1549
VDD
BST
DH
LX
(RBST)*
(CNL)*
DBST
CBST
CBYP
INPUT (VIN)
NH
L
VDD
DL
GND
NL
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING-NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry