參數(shù)資料
型號: MAX19527EXE+
廠商: Maxim Integrated Products
文件頁數(shù): 21/30頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 8CH 50MSPS 144CTBGA
應(yīng)用說明: Ultrasound Imaging Systems Application Note
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 240
位數(shù): 12
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 2.96W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-TFBGA
供應(yīng)商設(shè)備封裝: 144-CTFBGA
包裝: 管件
輸入數(shù)目和類型: 16 個單端,單極;8 個差分,單極
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
28
Grounding, Bypassing, and Board Layout
The ADC requires high-speed board layout design tech-
niques to achieve optimal dynamic performance. Refer
to the MAX19527 EV kit data sheet for a board layout
reference. Locate all bypass capacitors as close as
possible to the device, preferably on the same side as
the ADC, using surface-mount components for minimum
inductance. Bypass the AVDD and OVDD inputs with a
separate 0.1FF ceramic capacitor to GND at both sides
of the device (row A and row M). Bypass CMOUT with
a 1FF ceramic capacitor to GND. To use the internal
reference, bypass REFIO with a 0.1FF ceramic capacitor
to GND. For optimal performance using either an internal
or external reference, bypass REFH to REHL with a 0.1FF
ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. Isolate the
ground plane from any noisy digital system ground
planes. Route high-speed digital signal traces away from
sensitive analog traces. Keep all signal lines short and
free of 90N turns.
Ensure that the differential analog input network layout is
symmetric and that all parasitics are balanced equally.
Ensure that the LVDS outputs are routed as matched
length, 100I terminated, differential transmission lines.
Refer to the MAX19527 EV kit data sheet for an example
of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best-fit straight line. Worst-case deviation is
defined as INL.
Differential Nonlinearity (DNL)
DNL is the difference between the measured transfer-
function step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. DNL
deviations are measured at each step of the transfer
function and the worst-case deviation is defined as DNL.
Offset Error
Offset error is a parameter that indicates how well
the actual transfer function matches the ideal transfer
function at midscale. Ideally, the midscale transition
occurs at 0.5 LSB above midscale. The offset error is
the amount of deviation between the measured midscale
transition point and the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well
the slope of the measured transfer function matches
the slope of the ideal transfer function based on the
specified full-scale input voltage range. The gain error
is defined as the relative error of the measured transfer
function and is expressed as a percentage.
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter, a
small signal is defined as a single tone with an amplitude
less than -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the converter
and can be used to help calculate the overall noise
figure of a receive channel.
Near-Carrier Signal-to-Noise Ratio (NCSNR)
Near-carrier SNR is defined as the ratio of the power
in a near full-scale sinusoidal signal to the noise power
measured at 1kHz offset from the signal. The noise
power is normalized to 1Hz bandwidth. The near-carrier
noise measured in a single ADC channel can be corre-
lated to the near-carrier noise in other channels in a mul-
tichannel ADC. If that is the case, if output signals from
multiple channels are summed, the addition process does
not provide full processing gain of 10 x log(N), where
N is the number of channels. Near-carrier SNR for an
8-channel coherent sum is defined for the case of apply-
ing an in-phase sinusoidal signal to all 8 ADC channels,
and computing the near-carrier SNR for the digital sum
of all eight outputs.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digi-
tal samples, the theoretical maximum SNR is the ratio
of the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution (N bits):
SNRdB[MAX] = 6.02dB x N + 1.76dB
In reality, there are other noise sources besides quantiza-
tion noise (e.g., thermal noise, reference noise, clock jitter,
etc.). SNR is computed by taking the ratio of the RMS signal
to the RMS noise. RMS noise includes all spectral compo-
nents to the Nyquist frequency excluding the fundamental,
the first six harmonics (HD2–HD7), and the DC offset.
RMS
SIGNAL
SNR 20 log
NOISE
=
×
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