參數(shù)資料
型號： MAX19700ETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 30/32頁
文件大?。?/td> 0K
描述： IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 10
通道數(shù)： 2
功率（瓦特）： 36.3mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 48-WFQFN 裸露焊盤
供應商設備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33F. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Q-DAC DATA to CLK Rise Setup
Time
tDSQ
Figure 5 (Note 6)
10
ns
CLK Fall to I-DAC Data Hold Time
tDHI
Figure 5 (Note 6)
0
ns
CLK Rise to Q-DAC Data Hold
Time
tDHQ
Figure 5 (Note 6)
0
ns
CLK Duty Cycle
50
%
CLK Duty-Cycle Variation
±15
%
Digital Output Rise/Fall Time
20% to 80%
2.3
ns
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6)
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
10
ns
DIN to SCLK Setup Time
tDS
10
ns
DIN to SCLK Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
25
ns
SCLK Pulse-Width Low
tCL
25
ns
SCLK Period
tCP
50
ns
SCLK to CS Setup Time
tCS
10
ns
CS High Pulse Width
tCSW
80
ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
75
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
25
s
From idle to Rx mode with CLK present
during idle, ADC settles to within 1dB SINAD
7.3
Idle Wake-Up Time (With CLK)
tWAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
5
s
From standby to Rx mode, ADC settles to
within 1dB SINAD
7.3
Standby Wake-Up Time
tWAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error
25
s
Enable Time from Tx to Rx, (Ext2-
Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx,
and SPI4-Tx to SPI3-Rx Modes)
tENABLE, RX ADC settles to within 1dB SINAD
500
ns
Enable Time from Rx to Tx, (Ext1-
Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx,
and SPI3-Rx to SPI4-Tx Modes)
tENABLE, TX DAC settles to within 10 LSB error
1
s
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