參數(shù)資料
型號： MAX19700ETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 8/32頁
文件大?。?/td> 0K
描述： IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 10
通道數(shù)： 2
功率（瓦特）： 36.3mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 48-WFQFN 裸露焊盤
供應商設備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
16
______________________________________________________________________________________
and IAN, as well as QAP and QAN, and set the input
signal common-mode voltage within the ADC range of
VDD/ 2 (±200mV) for optimum performance.
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, DR indicator, and the resulting output data.
Channel I (CHI) and channel Q (CHQ) are sampled on
the rising edge of the clock signal (CLK) and the result-
ing data is multiplexed at the D0–D9 outputs. CHI data
is updated on the rising edge and CHQ data is updat-
ed on the falling edge of the CLK. The DR indicator fol-
lows CLK with a typical delay time of 8.5ns and remains
high when CHI data is updated and low when CHQ
data is updated. Including the delay through the output
latch, the total clock-cycle latency is 5 clock cycles for
CHI and 5.5 clock cycles for CHQ.
Digital Input/Output Data (D0–D9)
D0–D9 are the Rx ADC digital logic outputs when the
MAX19700 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic
inputs when the MAX19700 is in transmit mode. The
logic level is set by OVDD from 1.8V to VDD. The digital
output coding is offset binary (Table 1). Keep the
capacitive load on the digital outputs D0–D9 as low as
possible (<15pF) to avoid large digital currents feeding
back into the analog portion of the MAX19700 and
degrading its dynamic performance. Buffers on the dig-
ital outputs isolate the outputs from heavy capacitive
loads. Adding 100 resistors in series with the digital
outputs close to the MAX19700 will help improve ADC
performance. See the MAX19700EVKIT schematic for
an example of the digital outputs driving a digital buffer
through 100 series resistors.
During SHDN, IDLE, and STBY states, the pins D0–D9
are internally pulled up to prevent floating digital inputs.
To ensure no current flows through D0–D9 I/O, the
external bus needs to be either tri-stated or pulled up to
OVDD and should not be pulled to ground.
Dual 10-Bit Tx DAC and Transmit Path
The dual 10-bit digital-to-analog converters (Tx DAC)
operate with clock speeds up to 7.5MHz. The Tx DAC
digital inputs, D0–D9, are multiplexed on a single 10-bit
bus. The voltage reference determines the Tx path full-
scale output voltage. See the Reference Configurations
section for details on setting the reference voltage. Each
Tx path channel integrates a lowpass filter tuned to
meet the TD-SCDMA spectral mask requirements. The
TD-SCDMA filters are tuned for 1.27MHz cutoff frequen-
cy and >55dB image rejection at fIMAGE = 4.32MHz,
fOUT = 800kHz, and fCLK = 5.12MHz. See Figure 4 for
an illustration of the filter frequency response.
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGE
DIFFERENTIAL INPUT (LSB)
OFFSET BINARY (D0–D9)
OUTPUT DECIMAL CODE
VREF x 512/512
511 (+Full Scale – 1 LSB)
11 1111 1111
1023
VREF x 511/512
510 (+Full Scale – 2 LSB)
11 1111 1110
1022
VREF x 1/512
+1
10 0000 0001
513
VREF x 0/512
0 (Bipolar Zero)
10 0000 0000
512
-VREF x 1/512
-1
01 1111 1111
511
-VREF x 511/512
-511 (-Full Scale +1 LSB)
00 0000 0001
1
-VREF x 512/512
-512 (-Full Scale)
00 0000 0000
0
Figure 2. ADC Transfer Function
INPUT VOLTAGE (LSB)
-1
-510 -509
1024
2 x VREF
1 LSB =
VREF = VREFP - VREFN
VREF
V
REF
V
REF
0+ 1
-511
+510
+512
+511
-512
+509
(COM)
OFFSET
BINAR
Y
OUTPUT
CODE
(LSB)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0011
11 1111 1111
11 1111 1110
11 1111 1101
01 1111 1111
10 0000 0000
10 0000 0001
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相關代理商/技術參數(shù)
參數(shù)描述
MAX19700EVCMOD2 功能描述:ADC / DAC多通道 Evaluation Kit/Evaluation System for the MAX19700 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19700EVKIT 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19705ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM+ 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM+GH7 功能描述:ADC / DAC多通道 10-Bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
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