參數(shù)資料
型號: MAX19708ETM+
廠商: Maxim Integrated Products
文件頁數(shù): 36/37頁
文件大?。?/td> 0K
描述: IC ANLG FRONT END 11MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 43
位數(shù): 10
通道數(shù): 4
功率(瓦特): 36.9mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
8
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS High to DOUT Low (Aux-ADC
Conversion Time)
tCONV
Bit AD0 set, no averaging (see Table 15),
fCLK = 11MHz,
CLK divider = 4 (see Table 16)
4.36
s
DOUT Low to
CS Setup Time
tDCS
Bit AD0, AD10 set
200
ns
SCLK Low to DOUT Data Out
tCD
Bit AD0, AD10 set
14.5
ns
CS High to DOUT High Impedance
tCHZ
Bit AD0, AD10 set
200
ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
82.2
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
29
s
From idle to Rx mode with CLK present
during idle, ADC settles to within 1dB SINAD
9.6
Idle Wake-Up Time (With CLK)
tWAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
7.6
s
From standby to Rx mode, ADC settles to
within 1dB SINAD
17.5
Standby Wake-Up Time
tWAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error
24
s
Enable Time from Tx to Rx (Ext2-Tx
to Ext2-Rx, Ext4-Tx to Ext4-Rx, and
SPI4-Tx to SPI3-Rx States)
tENABLE, RX ADC settles to within 1dB SINAD
500
ns
Enable Time from Rx to Tx (Ext1-Rx
to Ext1-Tx, Ext4-Rx to Ext4-Tx, and
SPI3-Rx to SPI4-Tx States)
tENABLE, TX DAC settles to within 10 LSB error
500
ns
Enable Time from Tx to Rx (Ext1-Tx
to Ext1-Rx, Ext3-Tx to Ext3-Rx, and
SPI1-Tx to SPI1-Rx States)
tENABLE, RX ADC settles to within 1dB SINAD
8.1
s
Enable Time from Rx to Tx (Ext2-Rx
to Ext2-Tx, Ext3-Rx to Ext3-Tx, and
SPI1-Rx to SPI2-Tx States)
tENABLE,TX
DAC settles to within 10 LSB error
7.0
s
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)
Positive Reference
VREFP - VCOM
0.256
V
Negative Reference
VREFN - VCOM
-0.256
V
Common-Mode Output Voltage
VCOM
VDD / 2
- 0.15
VDD / 2
+ 0.15
V
Maximum REFP/REFN/COM
Source Current
ISOURCE
2mA
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