- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2009 > MAX19711ETN+T (Maxim Integrated Products)IC ANLG FRNT END 56-TQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | MAX19711ETN+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 19/36頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ANLG FRNT END 56-TQFN |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jun/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 37.5mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
MAX19711
10-Bit, 11Msps, Full-Duplex
Analog Front-End
26
______________________________________________________________________________________
sequence. SCLK can idle either high or low between tran-
sitions. Figure 7 shows the detailed timing diagram of the
3-wire serial interface.
Mode-Recovery Timing
Figure 8 shows the mode-recovery timing diagram.
tWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering Rx, Tx, or FD mode.
tENABLE is the recovery time when switching between
either Rx or Tx mode. tWAKE or tENABLE is the time for
the Rx ADC to settle within 1dB of specified SINAD per-
formance and Tx DAC settling to 10 LSB error. tWAKE
and tENABLE times are measured after either the 16-bit
serial command is latched into the MAX19711 by a
CS/WAKE transition high. In FAST mode, the recovery
time is 0.1s to switch to Rx mode and 1s to switch to
Tx mode.
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
by OVDD from 1.8V to VDD. Since the interstage conver-
sion of the device depends on the repeatability of the
rising and falling edges of the external clock, use a
clock with low jitter and fast rise and fall times (< 2ns).
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
Clock jitter is especially critical for undersampling appli-
cations. Consider the clock input as an analog input
and route away from any analog input or other digital
signal lines. The MAX19711 clock input operates with
an OVDD / 2 voltage threshold and accepts a 50%
±15% duty cycle.
When the clock signal is stopped at CLK input (CLK =
0V or OVDD), all internal registers hold their last value
and the MAX19711 saves the last power-management
mode or Tx/Rx/FD command. All converter circuits (Rx
ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last
value. When the clock signal is restarted at CLK, allow
7.2s (clock wake-up time) for the internal clock circuit-
ry to settle before updating the Tx DAC, reading a valid
Rx ADC conversion result, or starting an aux-ADC con-
version. This ensures the converters (Rx ADC, Tx DAC,
aux-ADC) meet all dynamic performance specifications.
The aux-DAC channels are not dependent on CLK, so
they may be updated when CLK is idle.
12-Bit, Auxiliary Control DACs
The MAX19711 includes three 12-bit aux-DACs (DAC1,
DAC2, DAC3) with 1s settling time for controlling vari-
able-gain amplifier (VGA), automatic gain-control
(AGC), and automatic frequency-control (AFC) func-
tions. The aux-DAC output range is 0.2V to 2.57V as
defined by VOH - VOL. During power-up, the VGA and
AGC outputs (DAC2 and DAC3) are at zero. The AFC
DAC (DAC1) is at 1.1V during power-up. The aux-DACs
can be independently controlled through the SPI bus,
except during SHDN mode where the aux-DACs are
turned off completely and the output voltage is set to
zero. In STBY and IDLE modes the aux-DACs maintain
the last value. On wake-up from SHDN, the aux-DACs
resume the last values.
Loading on the aux-DAC outputs should be carefully
observed to achieve specified settling time and stabili-
ty. The capacitive load must be kept to a maximum of
5pF including package and trace capacitance. The
log
SNR
ft
=×
××
×
20
1
2
π
IN
AJ
Figure 8. Mode-Recovery Timing Diagram
CS/WAKE
SCLK
DIN
16-BIT SERIAL DATA INPUT
AD0–AD9
ID/QD
DAC ANALOG OUTPUT
SETTLES TO 10 LSB ERROR
ADC DIGITAL OUTPUT SINAD
SETTLES TO WITHIN 1dB
tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX
tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX19712ETN+T | IC ANLG FRNT END 56-TQFN |
| MAX19713ETN+T | IC ANLG FRNT END 56-TQFN |
| MAX271ENG+ | IC FILTER LOWPASS PROG 24-DIP |
| MAX274ACWI+T | IC FILTER ANALOG 8TH-ORD 28SOIC |
| MAX281AEWE+ | IC FILTER 5TH-ORD BESSEL 16-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19711EVCMODU+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19711EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19711EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19712ETN | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19712ETN+ | 功能描述:ADC / DAC多通道 22Msps CODEC/AFE Full Duplex RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。